On Tuesday 08 June 2010, Matthew wrote: > So here's what I have found so far. When executing SEI, one more > instruction can execute before the first interrupt is serviced. When > enabling interrupts by restoring the status register, interrupts can > occur immediately. When writing to SPL, interrupts are automatically > disabled until the next memory write (up to 4 cycles). Interesting info!
Can you provide the sources for that or did you test it yourself? And do these statements hold for xmega en mega alike? > Therefore, the prologue and epilogue do not need to disable interrupts > at all. A write to SPL followed by a write to SPH should be interrupt > safe. I have not tested this yet. This seems hard to test, but is also very interesting. Ruud _______________________________________________ AVR-libc-dev mailing list AVR-libc-dev@nongnu.org http://lists.nongnu.org/mailman/listinfo/avr-libc-dev
