enabling SION bit makes SDHC1 working on the i.MX25.
tested on cpuimx25 board :
barebox@Eukrea CPUIMX25:/ mci0.probe=1
mci@mci0: registered disk0
barebox@Eukrea CPUIMX25:/ mkdir /mnt
barebox@Eukrea CPUIMX25:/ mount /dev/disk0.0 fat /mnt/
barebox@Eukrea CPUIMX25:/ devinfo mci0
resources:
driver: mci
Card:
Attached is an SD Card (Version: 2.0)
Capacity: 3826 MiB
High capacity card
CID: 1B534D30-30303030-107EA01B-4700AC00
CSD: 400E0032-5B590000-1DE37F80-0A404000
Max. transfer speed: 25000000 Hz
Manufacturer ID: 1B
OEM/Application ID: 534D
Product name: '00000'
Product revision: 1.0
Serial no: 2124421959
Manufacturing date: 12.2010
Parameters:
probe = 1
Signed-off-by: Eric Bénard <[email protected]>
---
arch/arm/mach-imx/include/mach/iomux-mx25.h | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx25.h
b/arch/arm/mach-imx/include/mach/iomux-mx25.h
index 58761b5..5010816 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx25.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx25.h
@@ -361,26 +361,26 @@
#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0,
NO_PAD_CTRL)
#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0,
NO_PAD_CTRL)
-#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x00, 0, 0,
PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0,
PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2,
NO_PAD_CTRL)
#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x05, 0, 0,
NO_PAD_CTRL)
-#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0,
PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0,
PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2,
NO_PAD_CTRL)
#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0,
NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x00, 0, 0,
PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0,
PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_DATA0__GPIO_2_25 IOMUX_PAD(0x390, 0x198, 0x05, 0, 0,
NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0,
PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0,
PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0,
NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0,
NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0,
PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0,
PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2,
NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0,
NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0,
PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0,
PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2,
NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0,
NO_PAD_CTRL)
--
1.7.7.6
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