Don't know where I got the 204MHZ previously, but
102MHz is the official supported maximum.

Signed-off-by: Lucas Stach <[email protected]>
---
Overclocking MSELECT by 100% seems to lead to
PCIe failures. Much more on T124 than on T30.
---
 drivers/clk/tegra/clk-tegra124.c | 2 +-
 drivers/clk/tegra/clk-tegra30.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 514b22a..3530127 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -286,7 +286,7 @@ static struct tegra_clk_init_table init_table[] = {
        {TEGRA124_CLK_PLL_P_OUT2,       TEGRA124_CLK_CLK_MAX,   48000000,       
1},
        {TEGRA124_CLK_PLL_P_OUT3,       TEGRA124_CLK_CLK_MAX,   102000000,      
1},
        {TEGRA124_CLK_PLL_P_OUT4,       TEGRA124_CLK_CLK_MAX,   204000000,      
1},
-       {TEGRA124_CLK_MSELECT,          TEGRA124_CLK_PLL_P,     204000000,      
1},
+       {TEGRA124_CLK_MSELECT,          TEGRA124_CLK_PLL_P,     102000000,      
1},
        {TEGRA124_CLK_UARTA,            TEGRA124_CLK_PLL_P,     0,              
1},
        {TEGRA124_CLK_UARTB,            TEGRA124_CLK_PLL_P,     0,              
1},
        {TEGRA124_CLK_UARTC,            TEGRA124_CLK_PLL_P,     0,              
1},
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 9997ab9..7210053 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -351,7 +351,7 @@ static struct tegra_clk_init_table init_table[] = {
        {TEGRA30_CLK_PLL_P_OUT2,        TEGRA30_CLK_CLK_MAX,    48000000,       
1},
        {TEGRA30_CLK_PLL_P_OUT3,        TEGRA30_CLK_CLK_MAX,    102000000,      
1},
        {TEGRA30_CLK_PLL_P_OUT4,        TEGRA30_CLK_CLK_MAX,    204000000,      
1},
-       {TEGRA30_CLK_MSELECT,           TEGRA30_CLK_PLL_P,      204000000,      
1},
+       {TEGRA30_CLK_MSELECT,           TEGRA30_CLK_PLL_P,      102000000,      
1},
        {TEGRA30_CLK_UARTA,             TEGRA30_CLK_PLL_P,      0,              
1},
        {TEGRA30_CLK_UARTB,             TEGRA30_CLK_PLL_P,      0,              
1},
        {TEGRA30_CLK_UARTC,             TEGRA30_CLK_PLL_P,      0,              
1},
-- 
1.9.3


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