>From this Linux commit:
commit 85de9d17c485c4196f74d45de2206d4802f8a3be
Author: Denis Carikli <[email protected]>
Date: Mon Apr 7 14:44:43 2014 +0200
imx-drm: match ipu_di_signal_cfg's clk_pol with its description.
According to the datasheet, setting the di0_polarity_disp_clk
field in the GENERAL di register sets the output clock polarity
to active high.
Signed-off-by: Denis Carikli <[email protected]>
Signed-off-by: Russell King <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
---
drivers/video/imx-ipu-v3/ipu-di.c | 2 +-
drivers/video/imx-ipu-v3/ipufb.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/imx-ipu-v3/ipu-di.c
b/drivers/video/imx-ipu-v3/ipu-di.c
index e3338d0..8df9c9f 100644
--- a/drivers/video/imx-ipu-v3/ipu-di.c
+++ b/drivers/video/imx-ipu-v3/ipu-di.c
@@ -627,7 +627,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct
ipu_di_signal_cfg *sig)
}
}
- if (!sig->clk_pol)
+ if (sig->clk_pol)
di_gen |= DI_GEN_POLARITY_DISP_CLK;
ipu_di_write(di, di_gen, DI_GENERAL);
diff --git a/drivers/video/imx-ipu-v3/ipufb.c b/drivers/video/imx-ipu-v3/ipufb.c
index 74c4dba..e804c31 100644
--- a/drivers/video/imx-ipu-v3/ipufb.c
+++ b/drivers/video/imx-ipu-v3/ipufb.c
@@ -100,7 +100,7 @@ int ipu_crtc_mode_set(struct ipufb_info *fbi,
sig_cfg.Vsync_pol = 1;
sig_cfg.enable_pol = 1;
- sig_cfg.clk_pol = 1;
+ sig_cfg.clk_pol = 0;
sig_cfg.width = mode->xres;
sig_cfg.height = mode->yres;
sig_cfg.h_start_width = mode->left_margin;
--
2.1.4
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