Split into separate function and only call it after the chip type
and revision is known.

Signed-off-by: Lucas Stach <l.st...@pengutronix.de>
---
 arch/arm/mach-imx/imx6.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index ba8fb8964ac8..07d3f57d8dcc 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -31,10 +31,8 @@ void imx6_init_lowlevel(void)
 {
        void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
        void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
-       void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
        bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
        bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D;
-       uint32_t val;
 
        /*
         * Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -94,6 +92,13 @@ void imx6_init_lowlevel(void)
                       MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
        }
 
+}
+
+void imx6_setup_ipu_qos(void)
+{
+       void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
+       uint32_t val;
+
        val = readl(iomux + IOMUXC_GPR4);
        val |= IMX6Q_GPR4_VPU_WR_CACHE_SEL | IMX6Q_GPR4_VPU_RD_CACHE_SEL |
                IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | 
IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
@@ -186,6 +191,8 @@ int imx6_init(void)
 
        imx_set_silicon_revision(cputypestr, mx6_silicon_revision);
 
+       imx6_setup_ipu_qos();
+
        return 0;
 }
 
-- 
2.8.1


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Reply via email to