Commit 1c33aacf8a247ab45814b43ac0ca903677afffae ("ARM: use memalign to
allocate page table"), reasonalby changed TTB allocation size from
SZ_32K to SZ_16K (TTB's real size), but it also changed alignment from
SZ_16K to SZ_64K for unclear reasons.
Reading various TTBR related ARM documentation it seems that worst
case alignment for it is 16KiB (bits [0, 13 - N] must be zero) which
also matches early TTB allocation code.
Since both early and regular MMU code has to share this paramter,
introduce ARM_TTB_SIZE and use it in both cases for both size and
alignment.
Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
---
arch/arm/cpu/mmu.c | 2 +-
arch/arm/include/asm/barebox-arm.h | 8 +++++++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 5f82b63ca..a89f420f2 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -469,7 +469,7 @@ static int mmu_init(void)
pr_crit("Critical Error: Can't request SDRAM region for
ttb at %p\n",
ttb);
} else {
- ttb = xmemalign(0x10000, 0x4000);
+ ttb = xmemalign(ARM_TTB_SIZE, ARM_TTB_SIZE);
}
pr_debug("ttb: 0x%p\n", ttb);
diff --git a/arch/arm/include/asm/barebox-arm.h
b/arch/arm/include/asm/barebox-arm.h
index f55c8bb0c..d97f68c54 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -32,6 +32,12 @@
#include <linux/compiler.h>
#include <asm/barebox-arm-head.h>
+/*
+ * We have a 4GiB address space split into 1MiB sections, with each
+ * section header taking 4 bytes
+ */
+#define ARM_TTB_SIZE (SZ_4G / SZ_1M * sizeof(u32))
+
unsigned long get_runtime_offset(void);
/* global_variable_offset() - Access global variables when not running at link
address
@@ -117,7 +123,7 @@ static inline unsigned long arm_mem_ttb(unsigned long
membase,
unsigned long endmem)
{
endmem = arm_mem_stack(membase, endmem);
- endmem = ALIGN_DOWN(endmem, SZ_16K) - SZ_16K;
+ endmem = ALIGN_DOWN(endmem, ARM_TTB_SIZE) - ARM_TTB_SIZE;
return endmem;
}
--
2.17.0
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