Move the setup of the shared- and fpgapins to its own function. These pins can only be configured and let out of reset after the FPGA has been programmed.
Signed-off-by: Steffen Trumtrar <[email protected]> --- arch/arm/boards/reflex-achilles/lowlevel.c | 1 + arch/arm/mach-socfpga/arria10-init.c | 49 +++++++++++++++------------- arch/arm/mach-socfpga/include/mach/generic.h | 2 ++ 3 files changed, 29 insertions(+), 23 deletions(-) diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c index fe57518cbba4..4c18fa6bca4f 100644 --- a/arch/arm/boards/reflex-achilles/lowlevel.c +++ b/arch/arm/boards/reflex-achilles/lowlevel.c @@ -26,6 +26,7 @@ static noinline void achilles_entry(void) setup_c(); arria10_init(&mainpll_cfg, &perpll_cfg, pinmux); + arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux); arria10_ddr_calibration_sequence(); diff --git a/arch/arm/mach-socfpga/arria10-init.c b/arch/arm/mach-socfpga/arria10-init.c index 2b968db5a12e..a1cc74c37413 100644 --- a/arch/arm/mach-socfpga/arria10-init.c +++ b/arch/arm/mach-socfpga/arria10-init.c @@ -123,6 +123,32 @@ static void arria10_mask_ecc_errors(void) writel(0x0007FFFF, ARRIA10_SYSMGR_ADDR + 0x94); } +void arria10_finish_io(struct arria10_mainpll_cfg *mainpll, + struct arria10_perpll_cfg *perpll, + uint32_t *pinmux) +{ + int i; + + /* shared pins */ + for (i = arria10_pinmux_shared_io_q1_1; + i <= arria10_pinmux_shared_io_q4_12; i++) + writel(pinmux[i], ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + + (i - arria10_pinmux_shared_io_q1_1) * sizeof(uint32_t)); + + /* usefpga: select source for signals: hps or fpga */ + for (i = arria10_pinmux_rgmii0_usefpga; + i < arria10_pinmux_max; i++) + writel(pinmux[i], ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + + (i - arria10_pinmux_rgmii0_usefpga) * sizeof(uint32_t)); + + arria10_reset_deassert_shared_peripherals(); + + arria10_reset_deassert_fpga_peripherals(); + + INIT_LL(); + + puts_ll("lowlevel init done\n"); +} /* * First C function to initialize the critical hardware early */ @@ -169,27 +195,4 @@ void arria10_init(struct arria10_mainpll_cfg *mainpll, /* deassert peripheral resets */ arria10_reset_deassert_dedicated_peripherals(); - - /* wait for fpga_usermode */ - while ((readl(0xffd03080) & 0x6) == 0); - - /* shared pins */ - for (i = arria10_pinmux_shared_io_q1_1; - i <= arria10_pinmux_shared_io_q4_12; i++) - writel(pinmux[i], ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + - (i - arria10_pinmux_shared_io_q1_1) * sizeof(uint32_t)); - - arria10_reset_deassert_shared_peripherals(); - - /* usefpga: select source for signals: hps or fpga */ - for (i = arria10_pinmux_rgmii0_usefpga; - i < arria10_pinmux_max; i++) - writel(pinmux[i], ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + - (i - arria10_pinmux_rgmii0_usefpga) * sizeof(uint32_t)); - - arria10_reset_deassert_fpga_peripherals(); - - INIT_LL(); - - puts_ll("lowlevel init done\n"); } diff --git a/arch/arm/mach-socfpga/include/mach/generic.h b/arch/arm/mach-socfpga/include/mach/generic.h index 9d6dd1f26cc6..da9028903cd5 100644 --- a/arch/arm/mach-socfpga/include/mach/generic.h +++ b/arch/arm/mach-socfpga/include/mach/generic.h @@ -13,6 +13,8 @@ struct arria10_pinmux_cfg; void arria10_init(struct arria10_mainpll_cfg *mainpll, struct arria10_perpll_cfg *perpll, uint32_t *pinmux); +void arria10_finish_io(struct arria10_mainpll_cfg *mainpll, + struct arria10_perpll_cfg *perpll, uint32_t *pinmux); void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config, struct socfpga_io_config *io_config); -- 2.11.0 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
