Port of a Linux commit dac29e6c5460d05774e3e8c4fdf4d6e7bd481fab Add a default DesignWare "link_up" test for use when a sub-driver doesn't supply its own pcie_host_ops.link_up() method.
[bhelgaas: changelog, split into its own patch] Signed-off-by: Joao Pinto <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Pratyush Anand <[email protected]> Signed-off-by: Andrey Smirnov <[email protected]> --- drivers/pci/pcie-designware.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c index ab6f1d289..d1c2635d6 100644 --- a/drivers/pci/pcie-designware.c +++ b/drivers/pci/pcie-designware.c @@ -72,6 +72,11 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C +/* PCIe Port Logic registers */ +#define PLR_OFFSET 0x700 +#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c) +#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010 + static unsigned long global_io_offset; int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) @@ -191,10 +196,13 @@ int dw_pcie_wait_for_link(struct pcie_port *pp) int dw_pcie_link_up(struct pcie_port *pp) { + u32 val; + if (pp->ops->link_up) return pp->ops->link_up(pp); - return 0; + val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); + return val & PCIE_PHY_DEBUG_R1_LINK_UP; } static inline struct pcie_port *host_to_pcie(struct pci_controller *host) -- 2.19.1 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
