Toggle GCTL.CORESOFTRESET before trying to access any of the block's registers. Without this additional step, first read of DWC3_GHWPARAMS* that follows results in assertion of GSTS.CSRTIMEOUT and IP block stuck in a non-functional state.
Note that all above has only been observerd on i.MX8MQ (ZII Zest board) for USB1 controller. USB2 doesn't seem to be affected by this. Signed-off-by: Andrey Smirnov <[email protected]> --- Changes since [v1]: - Dropped 100 ms delay [v1] http://lists.infradead.org/pipermail/barebox/2019-March/037501.html drivers/usb/dwc3/core.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 2e7031a34..60fd6318d 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -663,6 +663,25 @@ static void dwc3_check_params(struct dwc3 *dwc) } } +static void dwc3_coresoft_reset(struct dwc3 *dwc) +{ + u32 reg; + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg |= DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + /* + * Similar reset sequence in U-Boot has a 100ms delay here. In + * practice reset sequence seem to work as expected even + * without a delay. + */ + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); +} + static int dwc3_probe(struct device_d *dev) { struct dwc3 *dwc; @@ -695,6 +714,8 @@ static int dwc3_probe(struct device_d *dev) if (ret) return ret; + dwc3_coresoft_reset(dwc); + dwc3_cache_hwparams(dwc); ret = dwc3_core_init(dwc); -- 2.20.1 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
