On Tue, 2019-05-21 at 17:56 +0200, Ahmad Fatoum wrote: > From: Fabio Estevam <[email protected]> > > Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk > tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to > enter the ldb_di_ipu_div divider. If the divider gets locked up, no > ldb_di[x]_clk is generated, and the LVDS display will hang when the > ipu_di_clk is sourced from ldb_di_clk. > > To fix the problem, both the new and current parent of the ldb_di_clk > should be disabled before the switch. This patch ensures that correct > steps are followed when ldb_di_clk parent is switched in the beginning > of boot. The glitchy muxes are then registered as read-only. The clock > parent can be selected using the assigned-clocks and > assigned-clock-parents properties of the ccm device tree node: > > &clks { > assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, > <&clks IMX6QDL_CLK_LDB_DI1_SEL>; > assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>, > <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; > }; > > The issue is explained in detail in EB821 ("LDB Clock Switch Procedure & > i.MX6 Asynchronous Clock Switching Guidelines") [1]. > > [1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf > > Signed-off-by: Ranjani Vaidyanathan <[email protected]> > Signed-off-by: Fabio Estevam <[email protected]> > Signed-off-by: Philipp Zabel <[email protected]> > Reviewed-by: Akshay Bhat <[email protected]> > Tested-by Joshua Clayton <[email protected]> > Tested-by: Charles Kang <[email protected]> > Signed-off-by: Shawn Guo <[email protected]> > [afa: ported to barebox from Linux commit 5d283b0838] > Signed-off-by: Ahmad Fatoum <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]> regards Philipp _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
