At least some variants of the dwc watchdog controllers need the value 0x76 written to the counter restart register to actually take the value written to the Timeout range register. Happened on Rockchip RK3568, without this the watchdog immediately resets the system.
Signed-off-by: Sascha Hauer <[email protected]> --- drivers/watchdog/dw_wdt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c index 17771c7126..bc5d4a889a 100644 --- a/drivers/watchdog/dw_wdt.c +++ b/drivers/watchdog/dw_wdt.c @@ -111,6 +111,9 @@ static int dw_wdt_set_timeout(struct watchdog *wdd, unsigned int top_s) writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); + writel(WDOG_COUNTER_RESTART_KICK_VALUE, + dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET); + dw_wdt_start(wdd); return 0; -- 2.29.2 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
