SiFive SoCs have separate I-Caches that require self-modifying code like barebox' relocation and PBL extraction code to do cache maintenance. Implement sync_caches_for_execution and use it where appropriate.
The underlying fence.i primitive is part of the Zifencei (load/store fence) ISA extension. As we can't be sure it's always available, the exception handler will skip over the instruction if the CPU trips over it. Alternatively, if CONFIG_HAS_CACHE=n, the instruction won't be emitted at all. Signed-off-by: Ahmad Fatoum <[email protected]> --- arch/riscv/Kconfig.socs | 2 ++ arch/riscv/boot/uncompress.c | 2 ++ arch/riscv/cpu/core.c | 7 +++++++ arch/riscv/cpu/interrupts.c | 9 +++++++++ arch/riscv/include/asm/barebox-riscv.h | 2 ++ arch/riscv/include/asm/cacheflush.h | 16 ++++++++++++++++ arch/riscv/lib/reloc.c | 8 ++++++++ arch/riscv/lib/setupc.S | 2 ++ 8 files changed, 48 insertions(+) create mode 100644 arch/riscv/include/asm/cacheflush.h diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 8f955cd4d220..6ec2315d4e70 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -17,12 +17,14 @@ config SOC_VIRT bool "QEMU Virt Machine" select RISCV_S_MODE select BOARD_RISCV_GENERIC_DT + select HAS_CACHE help Generates an image tht can be be booted by QEMU. The image is called barebox-dt-2nd.img config CPU_SIFIVE bool + select HAS_CACHE config SOC_SIFIVE bool "SiFive SoCs" diff --git a/arch/riscv/boot/uncompress.c b/arch/riscv/boot/uncompress.c index c6c20b38e390..4ed9b4d37192 100644 --- a/arch/riscv/boot/uncompress.c +++ b/arch/riscv/boot/uncompress.c @@ -66,6 +66,8 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize, pbl_barebox_uncompress((void*)barebox_base, pg_start, pg_len); + sync_caches_for_execution(); + barebox = (void *)barebox_base; pr_debug("jumping to uncompressed image at 0x%p. dtb=0x%p\n", barebox, fdt); diff --git a/arch/riscv/cpu/core.c b/arch/riscv/cpu/core.c index 62eb0ca87164..b4727fe7449b 100644 --- a/arch/riscv/cpu/core.c +++ b/arch/riscv/cpu/core.c @@ -18,6 +18,7 @@ #include <linux/clk.h> #include <linux/err.h> #include <memory.h> +#include <asm/barebox-riscv.h> #include <asm-generic/memory_layout.h> #include <globalvar.h> #include <magicvar.h> @@ -91,3 +92,9 @@ static struct driver_d riscv_driver = { .of_compatible = riscv_dt_ids, }; postcore_platform_driver(riscv_driver); + +static void arch_shutdown(void) +{ + sync_caches_for_execution(); +} +archshutdown_exitcall(arch_shutdown); diff --git a/arch/riscv/cpu/interrupts.c b/arch/riscv/cpu/interrupts.c index df6d3e6e010b..0e8951b61968 100644 --- a/arch/riscv/cpu/interrupts.c +++ b/arch/riscv/cpu/interrupts.c @@ -121,6 +121,15 @@ unsigned long handle_trap(struct pt_regs *regs) if (skip_data_abort(regs)) goto skip; + if (regs->cause == 2) { /* illegal instruction */ + switch(*(unsigned long *)regs->epc) { + case 0x0000100f: /* fence.i */ + goto skip; + default: + break; + } + } + report_trap(regs); hang(); diff --git a/arch/riscv/include/asm/barebox-riscv.h b/arch/riscv/include/asm/barebox-riscv.h index bbe6cd040642..abb320242769 100644 --- a/arch/riscv/include/asm/barebox-riscv.h +++ b/arch/riscv/include/asm/barebox-riscv.h @@ -27,6 +27,8 @@ void setup_c(void); void relocate_to_current_adr(void); void relocate_to_adr(unsigned long target); +void sync_caches_for_execution(void); + void __noreturn __naked barebox_riscv_entry(unsigned long membase, unsigned long memsize, void *boarddata, unsigned int flags); diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h new file mode 100644 index 000000000000..9ff25740c66b --- /dev/null +++ b/arch/riscv/include/asm/cacheflush.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2015 Regents of the University of California + */ + +#ifndef _ASM_RISCV_CACHEFLUSH_H +#define _ASM_RISCV_CACHEFLUSH_H + +static inline void local_flush_icache_all(void) +{ +#ifdef HAS_CACHE + asm volatile ("fence.i" ::: "memory"); +#endif +} + +#endif /* _ASM_RISCV_CACHEFLUSH_H */ diff --git a/arch/riscv/lib/reloc.c b/arch/riscv/lib/reloc.c index 2fc8818cd698..479d586afdee 100644 --- a/arch/riscv/lib/reloc.c +++ b/arch/riscv/lib/reloc.c @@ -5,6 +5,7 @@ #include <linux/linkage.h> #include <asm/sections.h> #include <asm/barebox-riscv.h> +#include <asm/cacheflush.h> #include <debug_ll.h> #include <asm-generic/module.h> @@ -24,6 +25,11 @@ #define RISC_R_TYPE(x) ((x) & 0xFF) +void sync_caches_for_execution(void) +{ + local_flush_icache_all(); +} + void relocate_to_current_adr(void) { unsigned long offset; @@ -63,4 +69,6 @@ void relocate_to_current_adr(void) panic(""); } } + + sync_caches_for_execution(); } diff --git a/arch/riscv/lib/setupc.S b/arch/riscv/lib/setupc.S index 5fdd81c2c3ec..d225186c79fd 100644 --- a/arch/riscv/lib/setupc.S +++ b/arch/riscv/lib/setupc.S @@ -46,6 +46,8 @@ ENTRY(relocate_to_adr) jal __memcpy + jal sync_caches_for_execution + REG_L a0, (SZREG * 1)(sp) jr a0 /* jump to relocated address */ copied: -- 2.29.2 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
