DRAM setup on i.MX8MP is the same as on the i.MX8MP, except for DDRC_DDR_SS_GPR0, which the vendor's U-Boot port explicitly skips on the nano, irrespective of the configured DRAM type. Do likewise.
Signed-off-by: Ahmad Fatoum <[email protected]> --- drivers/ddr/imx8m/Kconfig | 2 +- drivers/ddr/imx8m/ddr_init.c | 8 +++++++- drivers/ddr/imx8m/ddrphy_utils.c | 1 + include/soc/imx8m/ddr.h | 2 ++ 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/imx8m/Kconfig b/drivers/ddr/imx8m/Kconfig index 7673ab5b4ccb..efc50c21d4c4 100644 --- a/drivers/ddr/imx8m/Kconfig +++ b/drivers/ddr/imx8m/Kconfig @@ -1,5 +1,5 @@ menu "i.MX8M DDR controllers" - depends on ARCH_IMX8MQ || ARCH_IMX8MM || ARCH_IMX8MP + depends on ARCH_IMX8MQ || ARCH_IMX8MM || ARCH_IMX8MN || ARCH_IMX8MP config IMX8M_DRAM bool "imx8m dram controller support" diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c index 34da44af6446..95ac76efcddb 100644 --- a/drivers/ddr/imx8m/ddr_init.c +++ b/drivers/ddr/imx8m/ddr_init.c @@ -48,6 +48,7 @@ static int imx8m_ddr_init(struct dram_timing_info *dram_timing, reg32_write(src_ddrc_rcr + 0x04, 0x8f000000); break; case DDRC_TYPE_MM: + case DDRC_TYPE_MN: case DDRC_TYPE_MP: reg32_write(src_ddrc_rcr, 0x8f00001f); reg32_write(src_ddrc_rcr, 0x8f00000f); @@ -88,7 +89,7 @@ static int imx8m_ddr_init(struct dram_timing_info *dram_timing, /* if ddr type is LPDDR4, do it */ tmp = reg32_read(DDRC_MSTR(0)); - if (tmp & (0x1 << 5)) + if (tmp & (0x1 << 5) && type != DDRC_TYPE_MN) reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ /* determine the initial boot frequency */ @@ -197,6 +198,11 @@ int imx8mm_ddr_init(struct dram_timing_info *dram_timing) return imx8m_ddr_init(dram_timing, DDRC_TYPE_MM); } +int imx8mn_ddr_init(struct dram_timing_info *dram_timing) +{ + return imx8m_ddr_init(dram_timing, DDRC_TYPE_MN); +} + int imx8mq_ddr_init(struct dram_timing_info *dram_timing) { return imx8m_ddr_init(dram_timing, DDRC_TYPE_MQ); diff --git a/drivers/ddr/imx8m/ddrphy_utils.c b/drivers/ddr/imx8m/ddrphy_utils.c index 6836e7d4b351..f47886116d14 100644 --- a/drivers/ddr/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx8m/ddrphy_utils.c @@ -343,6 +343,7 @@ static int dram_pll_init(u32 freq, enum ddrc_type type) case DDRC_TYPE_MQ: return dram_sscg_pll_init(freq); case DDRC_TYPE_MM: + case DDRC_TYPE_MN: case DDRC_TYPE_MP: return dram_frac_pll_init(freq); default: diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h index 78b15f1d461a..a25274c57671 100644 --- a/include/soc/imx8m/ddr.h +++ b/include/soc/imx8m/ddr.h @@ -365,11 +365,13 @@ extern struct dram_timing_info dram_timing; enum ddrc_type { DDRC_TYPE_MM, + DDRC_TYPE_MN, DDRC_TYPE_MQ, DDRC_TYPE_MP, }; int imx8mm_ddr_init(struct dram_timing_info *timing_info); +int imx8mn_ddr_init(struct dram_timing_info *timing_info); int imx8mq_ddr_init(struct dram_timing_info *timing_info); int imx8mp_ddr_init(struct dram_timing_info *timing_info); int ddr_cfg_phy(struct dram_timing_info *timing_info, enum ddrc_type type); -- 2.30.2 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
