type is ambiguous and can mean either DDR controller (SoC) type, DRAM type or firmware (1D/2D) type. Replace variables called type plainly, with more descriptive ddrc_type, dram_type and fw_type.
Signed-off-by: Ahmad Fatoum <[email protected]> --- drivers/ddr/imx8m/ddr_init.c | 12 +++---- drivers/ddr/imx8m/ddrphy_train.c | 4 +-- include/soc/imx8m/ddr.h | 54 ++++++++++++++++---------------- 3 files changed, 35 insertions(+), 35 deletions(-) diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c index 41e1fba38a52..f046ea52df7f 100644 --- a/drivers/ddr/imx8m/ddr_init.c +++ b/drivers/ddr/imx8m/ddr_init.c @@ -50,7 +50,7 @@ static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) #define IMX8M_SAVED_DRAM_TIMING_BASE 0x180000 int imx8m_ddr_init(struct dram_timing_info *dram_timing, - enum ddrc_type type) + enum ddrc_type ddrc_type) { unsigned long src_ddrc_rcr = MX8M_SRC_DDRC_RCR_ADDR; unsigned int tmp, initial_drate, target_freq; @@ -59,7 +59,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, pr_debug("start DRAM init\n"); /* Step1: Follow the power up procedure */ - switch (type) { + switch (ddrc_type) { case DDRC_TYPE_MQ: reg32_write(src_ddrc_rcr + 0x04, 0x8f00000f); reg32_write(src_ddrc_rcr, 0x8f00000f); @@ -81,7 +81,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, initial_drate = dram_timing->fsp_msg[0].drate; /* default to the frequency point 0 clock */ - ddrphy_init_set_dfi_clk(initial_drate, type); + ddrphy_init_set_dfi_clk(initial_drate, ddrc_type); /* D-aasert the presetn */ reg32_write(src_ddrc_rcr, 0x8F000006); @@ -107,7 +107,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, /* if ddr type is LPDDR4, do it */ tmp = reg32_read(DDRC_MSTR(0)); - if (tmp & (0x1 << 5) && type != DDRC_TYPE_MN) + if (tmp & (0x1 << 5) && ddrc_type != DDRC_TYPE_MN) reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ /* determine the initial boot frequency */ @@ -134,7 +134,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, */ pr_debug("ddrphy config start\n"); - ret = ddr_cfg_phy(dram_timing, type); + ret = ddr_cfg_phy(dram_timing, ddrc_type); if (ret) return ret; @@ -154,7 +154,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, reg32_write(DDRC_SWCTL(0), 0x00000000); /* Apply rank-to-rank workaround */ - update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1, type); + update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1, ddrc_type); /* Step16: Set DFIMISC.dfi_init_start to 1 */ setbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); diff --git a/drivers/ddr/imx8m/ddrphy_train.c b/drivers/ddr/imx8m/ddrphy_train.c index 2190b5341307..f739c6510703 100644 --- a/drivers/ddr/imx8m/ddrphy_train.c +++ b/drivers/ddr/imx8m/ddrphy_train.c @@ -93,7 +93,7 @@ void ddr_load_train_code(enum dram_type dram_type, enum fw_type fw_type) DDRC_PHY_DMEM, dmem, dsize); } -int ddr_cfg_phy(struct dram_timing_info *dram_timing, enum ddrc_type type) +int ddr_cfg_phy(struct dram_timing_info *dram_timing, enum ddrc_type ddrc_type) { struct dram_cfg_param *dram_cfg; struct dram_fsp_msg *fsp_msg; @@ -116,7 +116,7 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing, enum ddrc_type type) for (i = 0; i < dram_timing->fsp_msg_num; i++) { pr_debug("DRAM PHY training for %dMTS\n", fsp_msg->drate); /* set dram PHY input clocks to desired frequency */ - ddrphy_init_set_dfi_clk(fsp_msg->drate, type); + ddrphy_init_set_dfi_clk(fsp_msg->drate, ddrc_type); /* load the dram training firmware image */ dwc_ddrphy_apb_wr(0xd0000, 0x0); diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h index ad13632d28d9..e90adc37df87 100644 --- a/include/soc/imx8m/ddr.h +++ b/include/soc/imx8m/ddr.h @@ -333,6 +333,13 @@ enum dram_type { DRAM_TYPE_DDR4, }; +enum ddrc_type { + DDRC_TYPE_MM, + DDRC_TYPE_MN, + DDRC_TYPE_MQ, + DDRC_TYPE_MP, +}; + struct dram_cfg_param { unsigned int reg; unsigned int val; @@ -368,71 +375,64 @@ struct dram_timing_info { extern struct dram_timing_info dram_timing; -enum ddrc_type { - DDRC_TYPE_MM, - DDRC_TYPE_MN, - DDRC_TYPE_MQ, - DDRC_TYPE_MP, -}; - void ddr_get_firmware_lpddr4(void); void ddr_get_firmware_ddr(void); -static void ddr_get_firmware(enum dram_type type) +static void ddr_get_firmware(enum dram_type dram_type) { - if (type == DRAM_TYPE_LPDDR4) + if (dram_type == DRAM_TYPE_LPDDR4) ddr_get_firmware_lpddr4(); else ddr_get_firmware_ddr(); } int imx8m_ddr_init(struct dram_timing_info *dram_timing, - enum ddrc_type type); + enum ddrc_type ddrc_type); static inline int imx8mm_ddr_init(struct dram_timing_info *dram_timing, - enum dram_type type) + enum dram_type dram_type) { - ddr_get_firmware(type); + ddr_get_firmware(dram_type); return imx8m_ddr_init(dram_timing, DDRC_TYPE_MM); } static inline int imx8mn_ddr_init(struct dram_timing_info *dram_timing, - enum dram_type type) + enum dram_type dram_type) { - ddr_get_firmware(type); + ddr_get_firmware(dram_type); return imx8m_ddr_init(dram_timing, DDRC_TYPE_MN); } static inline int imx8mq_ddr_init(struct dram_timing_info *dram_timing, - enum dram_type type) + enum dram_type dram_type) { - ddr_get_firmware(type); + ddr_get_firmware(dram_type); return imx8m_ddr_init(dram_timing, DDRC_TYPE_MQ); } static inline int imx8mp_ddr_init(struct dram_timing_info *dram_timing, - enum dram_type type) + enum dram_type dram_type) { - ddr_get_firmware(type); + ddr_get_firmware(dram_type); return imx8m_ddr_init(dram_timing, DDRC_TYPE_MP); } -int ddr_cfg_phy(struct dram_timing_info *timing_info, enum ddrc_type type); +int ddr_cfg_phy(struct dram_timing_info *timing_info, enum ddrc_type ddrc_type); void load_lpddr4_phy_pie(void); void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); void dram_config_save(struct dram_timing_info *info, unsigned long base); /* utils function for ddr phy training */ int wait_ddrphy_training_complete(void); -void ddrphy_init_set_dfi_clk(unsigned int drate, enum ddrc_type type); -void ddrphy_init_read_msg_block(enum fw_type type); +void ddrphy_init_set_dfi_clk(unsigned int drate, enum ddrc_type ddrc_type); +void ddrphy_init_read_msg_block(enum fw_type fw_type); void update_umctl2_rank_space_setting(unsigned int pstat_num, - enum ddrc_type type); + enum ddrc_type ddrc_type); void get_trained_CDD(unsigned int fsp); #define reg32_write(a, v) writel(v, a) @@ -457,22 +457,22 @@ enum ddrc_phy_firmware_offset { DDRC_PHY_DMEM = 0x00054000U, }; -void ddr_load_train_code(enum dram_type dram_type, enum fw_type type); +void ddr_load_train_code(enum dram_type dram_type, enum fw_type fw_type); void ddrc_phy_load_firmware(void __iomem *, enum ddrc_phy_firmware_offset, const u16 *, size_t); -static inline bool dram_is_lpddr4(enum dram_type type) +static inline bool dram_is_lpddr4(enum dram_type dram_type) { return IS_ENABLED(CONFIG_FIRMWARE_IMX_LPDDR4_PMU_TRAIN) && - type == DRAM_TYPE_LPDDR4; + dram_type == DRAM_TYPE_LPDDR4; } -static inline bool dram_is_ddr4(enum dram_type type) +static inline bool dram_is_ddr4(enum dram_type dram_type) { return IS_ENABLED(CONFIG_FIRMWARE_IMX_DDR4_PMU_TRAIN) && - type == DRAM_TYPE_DDR4; + dram_type == DRAM_TYPE_DDR4; } #define DDRC_PHY_REG(x) ((x) * 4) -- 2.30.2
