Re: [PATCH 1/2] ARM: socfpga: Fix SDRAM firewall init

Tue, 01 Nov 2022 03:09:00 -0700 

Hi Ahmad,
The access of FPGA IPs to SDRAM regions is now possible. The region filters were already set correctly, only 'enable' bits were not. I split the fix into two patches, because they fix different sub-problems of one issue. 

Regards,
Slava

On 01.11.2022 10:58, Ahmad Fatoum wrote:

Hello Slava,

On 01.11.22 10:52, Vyacheslav Yurkov wrote:

From: Vyacheslav Yurkov <[email protected]>

Incorrect enable bits were used in initialization sequence of SDRAM
firewall

Thanks for your patch.

It'd be useful to know what implications the incorrect enable bits had.
What didn't work that now does?

Cheers,
Ahmad


Signed-off-by: Vyacheslav Yurkov <[email protected]>
---
  arch/arm/mach-socfpga/arria10-sdram.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/arria10-sdram.c 
b/arch/arm/mach-socfpga/arria10-sdram.c
index 35c355df71..b7eade0b17 100644
--- a/arch/arm/mach-socfpga/arria10-sdram.c
+++ b/arch/arm/mach-socfpga/arria10-sdram.c
@@ -486,7 +486,7 @@ static int arria10_sdram_firewall_setup(void)
        writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR);
        writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR);

  
-	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN;

+       mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN;
        writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);

  
  	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR);

@@ -494,7 +494,7 @@ static int arria10_sdram_firewall_setup(void)
        writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR);
        writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR);

  
-	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN;

+       mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN;
        writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);

  
  	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR);

@@ -502,7 +502,7 @@ static int arria10_sdram_firewall_setup(void)
        writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR);
        writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR);

  
-	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN;

+       mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN;
        writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);

  
  	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR);


























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