From: Kai Assman <[email protected]> Currently the ps_clk_rate is locked to 33.3MHz. The devicetree provides a property "ps-clock-frequency" that specifies this clock.
If the property is found, overwrite ps_clk_rate otherwise stay at the default 33.3MHz Signed-off-by: Kai Assmann <[email protected]> Signed-off-by: Steffen Trumtrar <[email protected]> --- drivers/clk/zynq/clkc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 8e4beda295..37a0fbadb5 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -388,6 +388,9 @@ static int zynq_clock_probe(struct device *dev) return PTR_ERR(parent_res); slcr_offset = parent_res->start; + + of_property_read_u32(dev->device_node, "ps-clock-frequency", + (u32 *)&ps_clk_rate); } iores = request_iomem_region(dev_name(dev), iores->start + slcr_offset, -- 2.39.0
