This driver initially started as a modification of dove-sdhci driver, it has been heavily reworked to be closer to rockchip-dwcmshc-sdhci by using more common sdhci code.
Signed-off-by: Jules Maselbas <[email protected]> --- drivers/mci/Kconfig | 8 + drivers/mci/Makefile | 1 + drivers/mci/dwcmshc-sdhci.c | 520 ++++++++++++++++++++++++++++++++++++ 3 files changed, 529 insertions(+) create mode 100644 drivers/mci/dwcmshc-sdhci.c diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig index bbdca67e9d..1fde0c8ffe 100644 --- a/drivers/mci/Kconfig +++ b/drivers/mci/Kconfig @@ -58,6 +58,14 @@ config MCI_MMC_GPP_PARTITIONS comment "--- MCI host drivers ---" +config MCI_DWC_MSHC + bool "Synopsys DesignWare Cores MSHC" + depends on HAS_DMA + select MCI_SDHCI + help + This selects support for the Synopsys DesignWare Mobile Storage Host Controller + block (DWC_mshc), this provides host support for SD/eMMC interfaces, in SDMA mode. + config MCI_DW bool "Synopsys DesignWare Memory Card Interface" depends on HAS_DMA diff --git a/drivers/mci/Makefile b/drivers/mci/Makefile index e3dc5ad8ae..35d11fb439 100644 --- a/drivers/mci/Makefile +++ b/drivers/mci/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_MCI_ROCKCHIP_DWCMSHC) += rockchip-dwcmshc-sdhci.o obj-$(CONFIG_MCI_TEGRA) += tegra-sdmmc.o obj-$(CONFIG_MCI_SPI) += mci_spi.o obj-$(CONFIG_MCI_DW) += dw_mmc.o +obj-$(CONFIG_MCI_DWC_MSHC) += dwcmshc-sdhci.o obj-$(CONFIG_MCI_MMCI) += mmci.o obj-$(CONFIG_MCI_STM32_SDMMC2) += stm32_sdmmc2.o obj-pbl-$(CONFIG_MCI_SDHCI) += sdhci.o diff --git a/drivers/mci/dwcmshc-sdhci.c b/drivers/mci/dwcmshc-sdhci.c new file mode 100644 index 0000000000..1e0af06f50 --- /dev/null +++ b/drivers/mci/dwcmshc-sdhci.c @@ -0,0 +1,520 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2019 Yann Sionneau, Kalray Inc. +// SPDX-FileCopyrightText: 2023 Jules Maselbas, Kalray Inc. + +#include <clock.h> +#include <common.h> +#include <init.h> +#include <io.h> +#include <dma.h> +#include <malloc.h> +#include <mci.h> +#include <linux/err.h> +#include <linux/clk.h> + +#include "sdhci.h" + +#define CARD_STATUS_MASK (0x1e00) +#define CARD_STATUS_TRAN (4 << 9) +static int dwcmshc_mci_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, + struct mci_data *data); + +struct dwcmshc_host { + struct mci_host mci; + struct sdhci sdhci; + unsigned int in_abort_sequence; +}; + +#define priv_from_mci_host(h) container_of(h, struct dwcmshc_host, mci) + +static inline int dwcmshc_sdma_supported(struct dwcmshc_host *host) +{ + return host->sdhci.caps & SDHCI_CAN_DO_SDMA; +} + +static inline void dwcmshc_write_dma_addr(struct dwcmshc_host *host, u64 addr) +{ + sdhci_write32(&host->sdhci, SDHCI_ADMA_ADDRESS, addr & 0xffffffff); + sdhci_write32(&host->sdhci, SDHCI_ADMA_ADDRESS_HI, addr >> 32); +} + +static inline u64 dwcmshc_read_dma_addr(struct dwcmshc_host *host) +{ + u64 addrh, addrl; + + addrl = sdhci_read32(&host->sdhci, SDHCI_ADMA_ADDRESS); + addrh = sdhci_read32(&host->sdhci, SDHCI_ADMA_ADDRESS_HI); + + return (addrh << 32) | addrl; +} + +static int dwcmshc_wait_for_done(struct dwcmshc_host *host, u16 mask) +{ + u16 status; + u64 start; + u64 addr; + + start = get_time_ns(); + while (1) { + status = sdhci_read16(&host->sdhci, SDHCI_INT_NORMAL_STATUS); + if (status & SDHCI_INT_ERROR) { + dev_err(host->mci.hw_dev, + "SDHCI_INT_ERROR, normal int status: %04x\n", + status); + return -EPERM; + } + /* this special quirk is necessary, as the dma + * engine stops on dma boundary and will only + * restart after acknowledging it this way. + */ + if (status & SDHCI_INT_DMA) { + sdhci_write16(&host->sdhci, SDHCI_INT_NORMAL_STATUS, SDHCI_INT_DMA); + addr = dwcmshc_read_dma_addr(host); + dwcmshc_write_dma_addr(host, addr); + } + if (status & mask) + break; + if (is_timeout(start, 10000 * MSECOND)) { + dev_err(host->mci.hw_dev, "SDHCI timeout while waiting for done\n"); + return -ETIMEDOUT; + } + } + return 0; +} + +static int dwcmshc_wait_for_status_mask(struct dwcmshc_host *host, + struct mci_cmd *cmd, u16 mask) +{ + int ret; + + ret = dwcmshc_wait_for_done(host, mask); + if (ret) { + dev_err(host->mci.hw_dev, "error on command %d\n", cmd->cmdidx); + dev_err(host->mci.hw_dev, "state = %04x %04x interrupt = %04x %04x\n", + sdhci_read16(&host->sdhci, SDHCI_PRESENT_STATE), + sdhci_read16(&host->sdhci, SDHCI_PRESENT_STATE1), + sdhci_read16(&host->sdhci, SDHCI_INT_NORMAL_STATUS), + sdhci_read16(&host->sdhci, SDHCI_INT_ERROR_STATUS)); + } + sdhci_write16(&host->sdhci, SDHCI_INT_NORMAL_STATUS, mask); + return ret; +} + +static void sdhci_rx_pio(struct sdhci *sdhci, struct mci_data *data, + unsigned int block) +{ + u32 *buf = (u32 *)data->dest; + int i; + + buf += block * data->blocksize / sizeof(u32); + + for (i = 0; i < data->blocksize / sizeof(u32); i++) + buf[i] = sdhci_read32(sdhci, SDHCI_BUFFER); +} + +static void sdhci_tx_pio(struct sdhci *sdhci, struct mci_data *data, + unsigned int block) +{ + const u32 *buf = (const u32 *)data->src; + int i; + + buf += block * data->blocksize / sizeof(u32); + + for (i = 0; i < data->blocksize / sizeof(u32); i++) + sdhci_write32(sdhci, SDHCI_BUFFER, buf[i]); +} + +static int dwcmshc_pio_xfer(struct dwcmshc_host *host, struct mci_cmd *cmd, + struct mci_data *data) +{ + unsigned int i; + u16 sts; + int ret; + + if (data->flags & MMC_DATA_READ) + sts = SDHCI_INT_DATA_AVAIL; + else + sts = SDHCI_INT_SPACE_AVAIL; + + for (i = 0; i < data->blocks; i++) { + ret = dwcmshc_wait_for_status_mask(host, cmd, sts); + if (ret) + return ret; + + if (data->flags & MMC_DATA_READ) + sdhci_rx_pio(&host->sdhci, data, i); + else + sdhci_tx_pio(&host->sdhci, data, i); + } + + return 0; +} + +static void mci_setup_cmd(struct mci_cmd *p, unsigned int cmd, unsigned int arg, + unsigned int response) +{ + p->cmdidx = cmd; + p->cmdarg = arg; + p->resp_type = response; +} + +static int do_abort_sequence(struct mci_host *mci, struct mci_cmd *current_cmd) +{ + int ret = 0; + struct dwcmshc_host *host = priv_from_mci_host(mci); + struct mci_cmd cmd; + u64 start; + + host->in_abort_sequence = 1; + + mci_setup_cmd(&cmd, MMC_CMD_STOP_TRANSMISSION, 0, MMC_RSP_R1b); + ret = dwcmshc_mci_send_cmd(mci, &cmd, NULL); + if (ret) { + dev_err(host->mci.hw_dev, "Abort failed at first cmd12!\n"); + goto out; + } + mci_setup_cmd(&cmd, MMC_CMD_SEND_STATUS, mci->mci->rca << 16, + MMC_RSP_R1); + ret = dwcmshc_mci_send_cmd(mci, &cmd, NULL); + if (ret) { + dev_err(host->mci.hw_dev, "Abort failed at first cmd13!\n"); + goto out; + } + + if ((cmd.response[0] & CARD_STATUS_MASK) == CARD_STATUS_TRAN) + goto out; /* All is OK! */ + + mci_setup_cmd(&cmd, MMC_CMD_STOP_TRANSMISSION, 0, MMC_RSP_R1b); + ret = dwcmshc_mci_send_cmd(mci, &cmd, NULL); + if (ret) { + dev_err(host->mci.hw_dev, "Abort failed at second cmd12!\n"); + goto out; + } + + mci_setup_cmd(&cmd, MMC_CMD_SEND_STATUS, mci->mci->rca << 16, + MMC_RSP_R1); + ret = dwcmshc_mci_send_cmd(mci, &cmd, NULL); + if (ret) { + dev_err(host->mci.hw_dev, "Abort failed at second cmd13!\n"); + goto out; + } + + if ((cmd.response[0] & CARD_STATUS_MASK) == CARD_STATUS_TRAN) { + goto out; /* All is OK! */ + } else { + dev_err(host->mci.hw_dev, + "Abort sequence failed to put card in TRAN state!\n"); + ret = 1; + goto out; + } + +out: + /* Perform SW reset if in abort sequence */ + sdhci_write8(&host->sdhci, SDHCI_SOFTWARE_RESET, + SDHCI_RESET_DATA | SDHCI_RESET_CMD); + start = get_time_ns(); + while (sdhci_read8(&host->sdhci, SDHCI_SOFTWARE_RESET) != 0) { + if (is_timeout(start, 50 * MSECOND)) { + dev_err(host->mci.hw_dev, + "SDHCI data reset timeout\n"); + break; + } + } + host->in_abort_sequence = 0; + return ret; +} + +static int dwcmshc_mci_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, + struct mci_data *data) +{ + struct dwcmshc_host *host = priv_from_mci_host(mci); + dma_addr_t dma = SDHCI_NO_DMA; + u32 mask, command, xfer; + int ret; + + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION + && host->in_abort_sequence == 0) + return do_abort_sequence(mci, cmd); + + /* Do not wait for CMD_INHIBIT_DAT on stop commands */ + mask = SDHCI_CMD_INHIBIT_CMD; + if (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION) + mask |= SDHCI_CMD_INHIBIT_DATA; + + /* Wait for bus idle */ + ret = wait_on_timeout(50 * MSECOND, + !(sdhci_read16(&host->sdhci, SDHCI_PRESENT_STATE) & mask)); + if (ret) { + dev_err(host->mci.hw_dev, "SDHCI timeout while waiting for idle\n"); + return -ETIMEDOUT; + } + + if (data) + dev_dbg(host->mci.hw_dev, "cmd %d arg %d bcnt %d bsize %d\n", + cmd->cmdidx, cmd->cmdarg, data->blocks, data->blocksize); + else + dev_dbg(host->mci.hw_dev, "cmd %d arg %d\n", cmd->cmdidx, cmd->cmdarg); + + sdhci_write32(&host->sdhci, SDHCI_INT_STATUS, ~0); + + /* setup transfer data */ + if (data) { + unsigned char hostctrl1; + hostctrl1 = sdhci_read8(&host->sdhci, SDHCI_HOST_CONTROL); + hostctrl1 &= ~SDHCI_CTRL_DMA_MASK; /* SDMA */ + sdhci_write8(&host->sdhci, SDHCI_HOST_CONTROL, hostctrl1); + + sdhci_setup_data_dma(&host->sdhci, data, &dma); + + if (dwcmshc_sdma_supported(host)) + dwcmshc_write_dma_addr(host, dma); + } + + sdhci_write8(&host->sdhci, SDHCI_TIMEOUT_CONTROL, 0xe); + + sdhci_set_cmd_xfer_mode(&host->sdhci, cmd, data, + dma == SDHCI_NO_DMA ? false : true, + &command, &xfer); + + sdhci_write16(&host->sdhci, SDHCI_TRANSFER_MODE, xfer); + + sdhci_write32(&host->sdhci, SDHCI_ARGUMENT, cmd->cmdarg); + sdhci_write16(&host->sdhci, SDHCI_COMMAND, command); + + ret = dwcmshc_wait_for_status_mask(host, cmd, SDHCI_INT_CMD_COMPLETE); + if (ret) + goto error; + + sdhci_read_response(&host->sdhci, cmd); + + if (data) { + if (dma_mapping_error(mci->hw_dev, dma)) { + ret = dwcmshc_pio_xfer(host, cmd, data); + if (ret) { + dev_err(host->mci.hw_dev, "error during PIO xfer\n"); + goto error; + } + } + ret = dwcmshc_wait_for_status_mask(host, cmd, + SDHCI_INT_XFER_COMPLETE); + if (ret) + goto error; + } + +error: + if (data && !dma_mapping_error(mci->hw_dev, dma)) { + u32 len = data->blocks * data->blocksize; + if (data->flags & MMC_DATA_READ) + dma_unmap_single(mci->hw_dev, dma, len, DMA_FROM_DEVICE); + else + dma_unmap_single(mci->hw_dev, dma, len, DMA_TO_DEVICE); + } + + if (ret) { + sdhci_reset(&host->sdhci, SDHCI_RESET_CMD); + sdhci_reset(&host->sdhci, SDHCI_RESET_DATA); + } + + sdhci_write32(&host->sdhci, SDHCI_INT_STATUS, ~0); + return ret; +} + +static u16 dwcmshc_get_clock_divider(struct dwcmshc_host *host, u32 reqclk) +{ + u16 div; + + for (div = 1; div < SDHCI_MAX_DIV_SPEC_300; div += 2) + if ((host->sdhci.max_clk / div) <= reqclk) + break; + div /= 2; + + return div; +} + +static void dwcmshc_mci_set_ios(struct mci_host *mci, struct mci_ios *ios) +{ + struct dwcmshc_host *host = priv_from_mci_host(mci); + u16 val; + + debug("%s: clock = %u, bus-width = %d, timing = %02x\n", __func__, + ios->clock, ios->bus_width, ios->timing); + + /* stop clock */ + sdhci_write16(&host->sdhci, SDHCI_CLOCK_CONTROL, 0); + + if (!ios->clock) + return; + + /* enable bus power */ + val = SDHCI_BUS_VOLTAGE_330; + sdhci_write8(&host->sdhci, SDHCI_POWER_CONTROL, val | SDHCI_BUS_POWER_EN); + udelay(400); + + /* set bus width */ + sdhci_set_bus_width(&host->sdhci, ios->bus_width); + + val = sdhci_read8(&host->sdhci, SDHCI_HOST_CONTROL); + if (ios->clock > 26000000) + val |= SDHCI_CTRL_HISPD; + else + val &= ~SDHCI_CTRL_HISPD; + sdhci_write8(&host->sdhci, SDHCI_HOST_CONTROL, val); + + /* set bus clock */ + sdhci_write16(&host->sdhci, SDHCI_CLOCK_CONTROL, 0); + val = dwcmshc_get_clock_divider(host, ios->clock); + val = SDHCI_CLOCK_INT_EN | SDHCI_FREQ_SEL(val) | ((val & 0x300) >> 2); + sdhci_write16(&host->sdhci, SDHCI_CLOCK_CONTROL, val); + + /* wait for internal clock stable */ + if (wait_on_timeout(20 * MSECOND, + sdhci_read16(&host->sdhci, SDHCI_CLOCK_CONTROL) + & SDHCI_CLOCK_INT_STABLE)) { + dev_err(host->mci.hw_dev, "SDHCI clock stable timeout\n"); + return; + } + + /* enable bus clock */ + sdhci_write16(&host->sdhci, SDHCI_CLOCK_CONTROL, val | SDHCI_CLOCK_CARD_EN); +} + +static int dwcmshc_mci_init(struct mci_host *mci, struct device *dev) +{ + struct dwcmshc_host *host = priv_from_mci_host(mci); + u16 ctrl2; + + /* reset mshci controller */ + sdhci_write8(&host->sdhci, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); + + /* wait for reset completion */ + if (wait_on_timeout(100 * MSECOND, + (sdhci_read8(&host->sdhci, SDHCI_SOFTWARE_RESET) + & SDHCI_RESET_ALL) == 0)) { + dev_err(dev, "SDHCI reset timeout\n"); + return -ETIMEDOUT; + } + + sdhci_write16(&host->sdhci, SDHCI_INT_ERROR_ENABLE, ~0); + sdhci_write16(&host->sdhci, SDHCI_INT_ENABLE, ~0); + sdhci_write32(&host->sdhci, SDHCI_INT_STATUS, ~0); + sdhci_write32(&host->sdhci, SDHCI_SIGNAL_ENABLE, ~0); + + /* Enable host version4 */ + ctrl2 = sdhci_read16(&host->sdhci, SDHCI_HOST_CONTROL2); + ctrl2 |= SDHCI_CTRL_V4_MODE; + sdhci_write16(&host->sdhci, SDHCI_HOST_CONTROL2, ctrl2); + + /* Enable 64-bit addressing */ + ctrl2 = sdhci_read16(&host->sdhci, SDHCI_HOST_CONTROL2); + ctrl2 |= SDHCI_CTRL_64BIT_ADDR; + sdhci_write16(&host->sdhci, SDHCI_HOST_CONTROL2, ctrl2); + + dev_dbg(host->mci.hw_dev, "host version4: %s\n", + ctrl2 & SDHCI_CTRL_V4_MODE ? "enabled" : "disabled"); + + return 0; +} + +static int dwcmshc_detect(struct device *dev) +{ + struct dwcmshc_host *host = dev->priv; + + return mci_detect_card(&host->mci); +} + +static int dwcmshc_mci_card_present(struct mci_host *mci) +{ + struct dwcmshc_host *host = priv_from_mci_host(mci); + u32 pstate; + + pstate = sdhci_read32(&host->sdhci, SDHCI_PRESENT_STATE); + return pstate & SDHCI_CARD_PRESENT; +} + +static void dwcmshc_set_dma_mask(struct device *dev) +{ + struct dwcmshc_host *host = dev->priv; + + if (host->sdhci.caps & SDHCI_CAN_64BIT_V4) + dma_set_mask(dev, DMA_BIT_MASK(64)); + else + dma_set_mask(dev, DMA_BIT_MASK(32)); +} + +static int dwcmshc_probe(struct device *dev) +{ + struct dwcmshc_host *host; + struct resource *iores; + struct mci_host *mci; + struct clk *clk; + int ret; + + host = xzalloc(sizeof(*host)); + mci = &host->mci; + + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); + goto err_mem_req; + } + + clk = clk_get(dev, NULL); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto err_clk_get; + } + clk_enable(clk); + + host->sdhci.base = IOMEM(iores->start); + host->sdhci.mci = mci; + host->sdhci.max_clk = clk_get_rate(clk); + + mci->hw_dev = dev; + mci->init = dwcmshc_mci_init; + mci->set_ios = dwcmshc_mci_set_ios; + mci->send_cmd = dwcmshc_mci_send_cmd; + mci->card_present = dwcmshc_mci_card_present; + + mci_of_parse(&host->mci); + sdhci_setup_host(&host->sdhci); + + mci->max_req_size = 0x8000; + mci->f_max = clk_get_rate(clk); + mci->f_min = mci->f_max / SDHCI_MAX_DIV_SPEC_300; + + dev->priv = host; + dev->detect = dwcmshc_detect; + + dwcmshc_set_dma_mask(dev); + + dev_dbg(host->mci.hw_dev, "host controller version: %u\n", + host->sdhci.version); + + ret = mci_register(&host->mci); + if (ret) + goto err_register; + + return ret; + +err_register: + clk_disable(clk); + clk_put(clk); +err_clk_get: + release_region(iores); +err_mem_req: + free(host); + + return ret; +} + +static struct of_device_id dwcmshc_dt_ids[] = { + { .compatible = "snps,dwcmshc-sdhci", }, + { } +}; + +static struct driver dwcmshc_driver = { + .name = "dwcmshc-sdhci", + .probe = dwcmshc_probe, + .of_compatible = DRV_OF_COMPAT(dwcmshc_dt_ids), +}; +device_platform_driver(dwcmshc_driver); -- 2.17.1
