This commit is based on Linux commit:
| commit 9ecf04016c87bcb33b44e24489d33618e2592f41
| Author: Wei Fang <wei.f...@nxp.com>
| Date: Thu Aug 18 11:00:54 2022 +0800
|
| net: phy: at803x: add disable hibernation mode support
|
| When the cable is unplugged, the Atheros AR803x PHYs will enter
| hibernation mode after about 10 seconds if the hibernation mode
| is enabled and will not provide any clock to the MAC. But for
| some MACs, this feature might cause unexpected issues due to the
| logic of MACs.
| Taking SYNP MAC (stmmac) as an example, if the cable is unplugged
| and the "eth0" interface is down, the AR803x PHY will enter
| hibernation mode. Then perform the "ifconfig eth0 up" operation,
| the stmmac can't be able to complete the software reset operation
| and fail to init it's own DMA. Therefore, the "eth0" interface is
| failed to ifconfig up. Why does it cause this issue? The truth is
| that the software reset operation of the stmmac is designed to
| depend on the RX_CLK of PHY.
| So, this patch offers an option for the user to determine whether
| to disable the hibernation mode of AR803x PHYs.
|
| Signed-off-by: Wei Fang <wei.f...@nxp.com>
| Reviewed-by: Andrew Lunn <and...@lunn.ch>
| Signed-off-by: Jakub Kicinski <k...@kernel.org>
The commit is adapted to always disable the hibernation mode instead of
making it optional since bootloaders require no special power
optimization.
Signed-off-by: Marco Felsch <m.fel...@pengutronix.de>
---
v2:
- adapt the commit message
- unconditional disable the hibernation mode (afa)
drivers/net/phy/at803x.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 2e3e57b27ee6..b9e11025b86c 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -32,6 +32,9 @@
#define AT803X_DEBUG_REG_5 0x05
#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
+#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
+#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15)
+
/* AT803x supports either the XTAL input pad, an internal PLL or the
* DSP as clock reference for the clock output pad. The XTAL reference
* is only used for 25 MHz output, all other frequencies need the PLL.
@@ -131,6 +134,15 @@ static int at803x_disable_tx_delay(struct phy_device
*phydev)
AT803X_DEBUG_TX_CLK_DLY_EN, 0);
}
+static int at803x_hibernation_mode_config(struct phy_device *phydev)
+{
+ /* The default after hardware reset is hibernation mode enabled. After
+ * software reset, the value is retained.
+ */
+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
+ AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
+}
+
static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id)
{
struct phy_driver *drv = to_phy_driver(phydev->dev.driver);
@@ -287,6 +299,10 @@ static int at803x_config_init(struct phy_device *phydev)
if (ret < 0)
return ret;
+ ret = at803x_hibernation_mode_config(phydev);
+ if (ret < 0)
+ return ret;
+
return 0;
}
--
2.39.2
