This part of code is not error proof and may fail depending on
implementation state of external HW. I hope this note help to find bugs
later.
Signed-off-by: Oleksij Rempel <o.rem...@pengutronix.de>
---
drivers/net/designware_eqos.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/net/designware_eqos.c b/drivers/net/designware_eqos.c
index 6caf3a436f..4489725e87 100644
--- a/drivers/net/designware_eqos.c
+++ b/drivers/net/designware_eqos.c
@@ -427,6 +427,10 @@ static int eqos_start(struct eth_device *edev)
if (ret)
return ret;
+ /* In some cases where PHY or DSA switch is the clock provider for
+ * EQOS, we need to probe and configure them before issuing software
+ * reset here.
+ */
setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
ret = readl_poll_timeout(&eqos->dma_regs->mode, mode_set,
--
2.39.2
