Currently, boards using the pca9450 pmic driver initialize the
RESET_CTRL register either in lowlevel.c or board.c explicitly to 0xA1
to enable the watchdog for Cold Reset with all voltage regulators
recycled except LDO1/ LDO2 in addition to the default configuration of
0x11 where the WDOG_B watchdog input is disabled.
Instead, enable the watchdog in the driver for Cold Reset with all
voltage regulators recycled except LDO1/ LDO2. When
nxp,wdog_b-warm-reset is set, the watchdog is instead enabled for Warm
Reset.
This is identical to U-Boot's behaviour since commit 910c7a881f5 ("pmic:
pca9450: Make warm reset on WDOG_B assertion") and Linux's since commit
2364a64d0673f ("regulator: pca9450: Make warm reset on WDOG_B
assertion").
Signed-off-by: Jonas Rebmann <[email protected]>
---
drivers/mfd/pca9450.c | 10 ++++++++++
include/mfd/pca9450.h | 4 ++++
2 files changed, 14 insertions(+)
diff --git a/drivers/mfd/pca9450.c b/drivers/mfd/pca9450.c
index
2511e662c3dfb5dfedbc461357ffa82d1812166f..5d5d3d8e017232a45676efad390a503500dd2156
100644
--- a/drivers/mfd/pca9450.c
+++ b/drivers/mfd/pca9450.c
@@ -103,6 +103,16 @@ static int __init pca9450_probe(struct device *dev)
/* Chip ID defined in bits [7:4] */
dev_info(dev, "PMIC Chip ID: 0x%x\n", (reg >> 4));
+ /* Enable WDOG_B, for cold reset by default */
+ if (of_property_read_bool(dev->of_node, "nxp,wdog_b-warm-reset"))
+ regmap_update_bits(regmap, PCA9450_RESET_CTRL,
+ PCA9450_PMIC_RESET_WDOG_B_CFG_MASK,
+ PCA9450_PMIC_RESET_WDOG_B_CFG_WARM);
+ else
+ regmap_update_bits(regmap, PCA9450_RESET_CTRL,
+ PCA9450_PMIC_RESET_WDOG_B_CFG_MASK,
+ PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12);
+
if (pca9450_init_callback)
pca9450_init_callback(regmap);
pca9450_map = regmap;
diff --git a/include/mfd/pca9450.h b/include/mfd/pca9450.h
index
7071c3a9da6c5adc26dbd6149fec5fa96f3365bf..af10e409855ff6c3585c7f63098a16e8ec33dee2
100644
--- a/include/mfd/pca9450.h
+++ b/include/mfd/pca9450.h
@@ -66,4 +66,8 @@ static inline int
pca9450_register_init_callback(void(*callback)(struct regmap *
}
#endif
+#define PCA9450_PMIC_RESET_WDOG_B_CFG_MASK 0xc0
+#define PCA9450_PMIC_RESET_WDOG_B_CFG_WARM 0x40
+#define PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12 0x80
+
#endif
--
2.39.5
