Instead of hardcoding the clock initialization in the clk-rk3568
driver, let's use the "assigned-clocks" device tree nodes to
configure the initial desired clock for the chip.
Inspecting the current settings shows that some clocks are already
defined in upstream dts, some don't need to be touched, and some
are initialized to the proper state by default.
The rest of the clock setup has been moved to the barebox rk3568.dtsi.
Tested on custom rk3568-based board.
Signed-off-by: Alexander Shiyan <eagle.alexander...@gmail.com>
---
arch/arm/dts/rk356x.dtsi | 21 +++++++++++++++++++++
drivers/clk/rockchip/clk-rk3568.c | 28 ----------------------------
2 files changed, 21 insertions(+), 28 deletions(-)
diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
index 995a9d5d92..5087c9cfce 100644
--- a/arch/arm/dts/rk356x.dtsi
+++ b/arch/arm/dts/rk356x.dtsi
@@ -3,6 +3,27 @@
#include <dt-bindings/soc/rockchip,boot-mode.h>
/ {
+ assigned-clocks =
+ <&cru CLK_SDMMC0>,
+ <&cru CCLK_EMMC>,
+ <&cru ACLK_BUS>,
+ <&cru PCLK_BUS>,
+ <&cru PCLK_TOP>,
+ <&cru PLL_APLL>,
+ <&cru PLL_NPLL>,
+ <&cru PLL_VPLL>;
+ assigned-clock-parents =
+ <&cru CPLL_50M>;
+ assigned-clock-rates =
+ <0>,
+ <200000000>,
+ <150000000>,
+ <100000000>,
+ <100000000>,
+ <816000000>,
+ <1200000000>,
+ <500000000>;
+
aliases {
pmugrf.reboot_mode = &reboot_mode_pmugrf;
pwm0 = &pwm0;
diff --git a/drivers/clk/rockchip/clk-rk3568.c
b/drivers/clk/rockchip/clk-rk3568.c
index bd6c8269ca..cdc7b99e47 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -1636,12 +1636,6 @@ static void __init rk3568_pmu_clk_init(struct
device_node *np)
ARRAY_SIZE(rk3568_pmucru_critical_clocks));
rockchip_clk_of_add_provider(np, ctx);
-
- clk_name_set_parent("ppll", "pll_ppll");
- clk_name_set_parent("clk_rtc_32k", "clk_rtc32k_frac");
- clk_name_set_rate("clk_rtc_32k", 32768);
- clk_name_set_rate("pclk_pmu", 100000000);
- clk_name_set_rate("pll_ppll", 200000000);
}
static void __init rk3568_clk_init(struct device_node *np)
@@ -1682,28 +1676,6 @@ static void __init rk3568_clk_init(struct device_node
*np)
ARRAY_SIZE(rk3568_cru_critical_clocks));
rockchip_clk_of_add_provider(np, ctx);
-
- clk_name_set_parent("npll", "pll_npll");
- clk_name_set_parent("vpll", "pll_vpll");
- clk_name_set_parent("pclk_bus", "gpll_100m");
- clk_name_set_parent("clk_sdmmc0", "cpll_50m");
- clk_name_set_parent("cclk_emmc", "gpll_200m");
-
- clk_name_set_rate("pll_cpll", 1000000000);
- clk_name_set_rate("pll_gpll", 1188000000);
- clk_name_set_rate("armclk", 600000000);
- clk_name_set_rate("aclk_bus", 150000000);
- clk_name_set_rate("pclk_bus", 100000000);
- clk_name_set_rate("aclk_top_high", 300000000);
- clk_name_set_rate("aclk_top_low", 200000000);
- clk_name_set_rate("hclk_top", 150000000);
- clk_name_set_rate("pclk_top", 100000000);
- clk_name_set_rate("aclk_perimid", 300000000);
- clk_name_set_rate("hclk_perimid", 150000000);
- clk_name_set_rate("pll_npll", 1200000000);
- clk_name_set_rate("pll_apll", 816000000);
-
- clk_name_set_parent("pclk_top", "gpll_100m");
}
struct clk_rk3568_inits {
--
2.39.1
