Linux writes this register unconditionally for all usdhc. As we didn't
seem to be hurt by its lack so far, we will set it only when
tuning support is enabled.
Signed-off-by: Ahmad Fatoum <a.fat...@pengutronix.de>
---
drivers/mci/imx-esdhc.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index 2bdd1532fe74..00b7e0693fcc 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -347,6 +347,21 @@ static int esdhc_init(struct mci_host *mci, struct device
*dev)
(host->socdata->flags & ESDHC_FLAG_STD_TUNING)) {
u32 tmp;
+ /*
+ * ROM code will change the bit burst_length_enable setting
+ * to zero if this usdhc is chosen to boot system. Change
+ * it back here, otherwise it will impact the performance a
+ * lot. This bit is used to enable/disable the burst length
+ * for the external AHB2AXI bridge. It's useful especially
+ * for INCR transfer because without burst length indicator,
+ * the AHB2AXI bridge does not know the burst length in
+ * advance. And without burst length indicator, AHB INCR
+ * transfer can only be converted to singles on the AXI side.
+ */
+ sdhci_write32(&host->sdhci, SDHCI_HOST_CONTROL,
+ sdhci_read32(&host->sdhci, SDHCI_HOST_CONTROL)
+ | ESDHC_BURST_LEN_EN_INCR);
+
/* disable DLL_CTRL delay line settings */
sdhci_write32(&host->sdhci, ESDHC_DLL_CTRL, 0x0);
--
2.39.5
