The AM62l device trees are based on the upstream submission which
currently lack the ethernet ports. Add them from the downstream Linux
repository.
Signed-off-by: Sascha Hauer <s.ha...@pengutronix.de>
---
arch/arm/dts/k3-am62l3-evm.dts | 78 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm/dts/k3-am62l3-evm.dts b/arch/arm/dts/k3-am62l3-evm.dts
index
16efb60bf326018cd483cdeae35ed9538d24d522..4484279e8fcc0361fe73bf42b63a0663b71725b7
100644
--- a/arch/arm/dts/k3-am62l3-evm.dts
+++ b/arch/arm/dts/k3-am62l3-evm.dts
@@ -12,6 +12,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am62l3.dtsi"
#include "k3-pinctrl.h"
@@ -105,6 +106,42 @@ eeprom@51 {
};
};
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_pins_default>,
+ <&rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy1>;
+};
+
+&cpsw3g_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default>;
+ status = "okay";
+
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+
+ cpsw3g_phy1: ethernet-phy@1 {
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
&i2c1 {
pinctrl-0 = <&i2c1_pins_default>;
pinctrl-names = "default";
@@ -201,6 +238,47 @@ AM62LX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B4)
MMC0_DAT7 */
bootph-all;
};
+ rgmii1_pins_default: rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0138, PIN_INPUT, 0) /* (Y8) RGMII1_RD0 */
+ AM62LX_IOPAD(0x013c, PIN_INPUT, 0) /* (AA6) RGMII1_RD1
*/
+ AM62LX_IOPAD(0x0140, PIN_INPUT, 0) /* (AA8) RGMII1_RD2
*/
+ AM62LX_IOPAD(0x0144, PIN_INPUT, 0) /* (W8) RGMII1_RD3 */
+ AM62LX_IOPAD(0x0134, PIN_INPUT, 0) /* (Y7) RGMII1_RXC */
+ AM62LX_IOPAD(0x0130, PIN_INPUT, 0) /* (Y6)
RGMII1_RX_CTL */
+ AM62LX_IOPAD(0x0120, PIN_OUTPUT, 0) /* (AC10)
RGMII1_TD0 */
+ AM62LX_IOPAD(0x0124, PIN_OUTPUT, 0) /* (W13) RGMII1_TD1
*/
+ AM62LX_IOPAD(0x0128, PIN_OUTPUT, 0) /* (Y11) RGMII1_TD2
*/
+ AM62LX_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AA11)
RGMII1_TD3 */
+ AM62LX_IOPAD(0x011c, PIN_OUTPUT, 0) /* (W11) RGMII1_TXC
*/
+ AM62LX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (AB11)
RGMII1_TX_CTL */
+ >;
+ };
+
+ rgmii2_pins_default: rgmii2-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0170, PIN_INPUT, 0) /* (AB9) RGMII2_RD0
*/
+ AM62LX_IOPAD(0x0174, PIN_INPUT, 0) /* (AC9) RGMII2_RD1
*/
+ AM62LX_IOPAD(0x0178, PIN_INPUT, 0) /* (AB10) RGMII2_RD2
*/
+ AM62LX_IOPAD(0x017c, PIN_INPUT, 0) /* (AB8) RGMII2_RD3
*/
+ AM62LX_IOPAD(0x016c, PIN_INPUT, 0) /* (AC7) RGMII2_RXC
*/
+ AM62LX_IOPAD(0x0168, PIN_INPUT, 0) /* (AC8)
RGMII2_RX_CTL */
+ AM62LX_IOPAD(0x0158, PIN_OUTPUT, 0) /* (AC12)
RGMII2_TD0 */
+ AM62LX_IOPAD(0x015c, PIN_OUTPUT, 0) /* (AB13)
RGMII2_TD1 */
+ AM62LX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AA12)
RGMII2_TD2 */
+ AM62LX_IOPAD(0x0164, PIN_OUTPUT, 0) /* (AA13)
RGMII2_TD3 */
+ AM62LX_IOPAD(0x0154, PIN_OUTPUT, 0) /* (Y13) RGMII2_TXC
*/
+ AM62LX_IOPAD(0x0150, PIN_OUTPUT, 0) /* (AB12)
RGMII2_TX_CTL */
+ >;
+ };
+
+ mdio1_pins_default: mdio1-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x014c, PIN_OUTPUT, 0) /* (AC15) MDIO0_MDC
*/
+ AM62LX_IOPAD(0x0148, PIN_INPUT, 0) /* (AC13) MDIO0_MDIO
*/
+ >;
+ };
+
mmc1_pins_default: mmc1-default-pins {
pinctrl-single,pins = <
AM62LX_IOPAD(0x0230, PIN_INPUT, 0) /* (Y3)
MMC1_CMD */
--
2.39.5
