[PATCH] ARM: Cortex-A9: document core versions used in various SoCs

[Lucas Stach]

The core revision is very helpful to know when checking if a specific
erratum is present in the core. Looking this up in the various SoC
specific documents is cumbersome, so leave a comment for the next time
anyone has to do this.

Signed-off-by: Lucas Stach <l.st...@pengutronix.de>
---
Tegra seems to miss some workarounds, fixing this requires a bit more
thought than I can spare right now.
---
 arch/arm/mach-imx/cpu_init.c                 | 2 ++
 arch/arm/mach-socfpga/cpu_init.c             | 2 ++
 arch/arm/mach-tegra/tegra_maincomplex_init.c | 2 ++
 arch/arm/mach-zynq/cpu_init.c                | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
index e9f42945528e..bd464e9f09e9 100644
--- a/arch/arm/mach-imx/cpu_init.c
+++ b/arch/arm/mach-imx/cpu_init.c
@@ -38,6 +38,8 @@ void imx6_cpu_lowlevel_init(void)
        arm_cpu_lowlevel_init();
 
        arm_early_mmu_cache_invalidate();
+
+       /* apply necessary workarounds for Cortex A9 r2p10 */
        enable_arm_errata_742230_war();
        enable_arm_errata_743622_war();
        enable_arm_errata_751472_war();
diff --git a/arch/arm/mach-socfpga/cpu_init.c b/arch/arm/mach-socfpga/cpu_init.c
index f10cd468da96..bed0dabc38e4 100644
--- a/arch/arm/mach-socfpga/cpu_init.c
+++ b/arch/arm/mach-socfpga/cpu_init.c
@@ -9,6 +9,8 @@
 void arria10_cpu_lowlevel_init(void)
 {
        arm_early_mmu_cache_invalidate();
+
+       /* apply necessary workarounds for Cortex A9 r4p1 */
        enable_arm_errata_794072_war();
        enable_arm_errata_845369_war();
 }
diff --git a/arch/arm/mach-tegra/tegra_maincomplex_init.c 
b/arch/arm/mach-tegra/tegra_maincomplex_init.c
index e4cc3e780cbe..2ffffcdee3ff 100644
--- a/arch/arm/mach-tegra/tegra_maincomplex_init.c
+++ b/arch/arm/mach-tegra/tegra_maincomplex_init.c
@@ -38,11 +38,13 @@ void tegra_maincomplex_entry(char *fdt)
        /* enable ARM errata workarounds early */
        switch (chiptype) {
        case TEGRA20:
+               /* Cortex A9 r1p1 */
                enable_arm_errata_716044_war();
                enable_arm_errata_742230_war();
                enable_arm_errata_751472_war();
                break;
        case TEGRA30:
+               /* Cortex A9 r2p9 */
                enable_arm_errata_743622_war();
                enable_arm_errata_751472_war();
                break;
diff --git a/arch/arm/mach-zynq/cpu_init.c b/arch/arm/mach-zynq/cpu_init.c
index f26e2947fd6a..b5f620004611 100644
--- a/arch/arm/mach-zynq/cpu_init.c
+++ b/arch/arm/mach-zynq/cpu_init.c
@@ -11,6 +11,8 @@ void zynq_cpu_lowlevel_init(void)
        arm_cpu_lowlevel_init();
 
        arm_early_mmu_cache_invalidate();
+
+       /* apply necessary workarounds for Cortex A9 r3p0 */
        enable_arm_errata_761320_war();
        enable_arm_errata_794072_war();
        enable_arm_errata_845369_war();
-- 
2.49.0