Cleanup the debug_ll code for SoCFPGA. The old Gen5 Socfpga have a
narrower ioport width for the NS16550. All newer generations support
32-bit access. Invert the logic and add new *_uart_putc functions for
use with pbl_set_putc.
Signed-off-by: Steffen Trumtrar <s.trumt...@pengutronix.de>
---
arch/arm/mach-socfpga/arria10-init.c | 2 +-
arch/arm/mach-socfpga/cyclone5-init.c | 2 +-
include/mach/socfpga/debug_ll.h | 44 +++++++++++++++++++++++------------
3 files changed, 31 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-socfpga/arria10-init.c
b/arch/arm/mach-socfpga/arria10-init.c
index
f8a15ec8b46a761904e470d66bd0900fdb0686ec..14cee3196ade7d36adbb1b70c5b0041bce3cc193
100644
--- a/arch/arm/mach-socfpga/arria10-init.c
+++ b/arch/arm/mach-socfpga/arria10-init.c
@@ -147,7 +147,7 @@ void arria10_finish_io(uint32_t *pinmux)
arria10_reset_deassert_fpga_peripherals();
- INIT_LL();
+ socfpga_uart_setup_ll();
puts_ll("lowlevel init done\n");
}
diff --git a/arch/arm/mach-socfpga/cyclone5-init.c
b/arch/arm/mach-socfpga/cyclone5-init.c
index
79a9b15d8761baa8b576a83871a06fbf0559ce91..63ec48b8e48d7e8daa9ce9c158ad5716739b9b3d
100644
--- a/arch/arm/mach-socfpga/cyclone5-init.c
+++ b/arch/arm/mach-socfpga/cyclone5-init.c
@@ -56,5 +56,5 @@ void socfpga_lowlevel_init(struct socfpga_cm_config
*cm_config,
writel(0x18, CYCLONE5_L3REGS_ADDRESS);
writel(0x1, 0xfffefc00);
- INIT_LL();
+ socfpga_uart_setup_ll();
}
diff --git a/include/mach/socfpga/debug_ll.h b/include/mach/socfpga/debug_ll.h
index
25b3581634704ac523b031a915b73408b674e0c5..698cca60373f7e382db12344e83925dbcb3b35aa
100644
--- a/include/mach/socfpga/debug_ll.h
+++ b/include/mach/socfpga/debug_ll.h
@@ -30,6 +30,26 @@
#define SCR 0x1c
#define THR 0x30
+static inline void socfpga_gen5_uart_putc(void *base, int c)
+{
+ /* Wait until there is space in the FIFO */
+ while ((readb(base + LSR) & LSR_THRE) == 0);
+ /* Send the character */
+ writeb(c, base + THR);
+ /* Wait to make sure it hits the line, in case we die too soon. */
+ while ((readb(base + LSR) & LSR_THRE) == 0);
+}
+
+static inline void socfpga_uart_putc(void *base, int c)
+{
+ /* Wait until there is space in the FIFO */
+ while ((readl(base + LSR) & LSR_THRE) == 0);
+ /* Send the character */
+ writel(c, base + THR);
+ /* Wait to make sure it hits the line, in case we die too soon. */
+ while ((readl(base + LSR) & LSR_THRE) == 0);
+}
+
#ifdef CONFIG_DEBUG_LL
static inline unsigned int ns16550_calc_divisor(unsigned int clk,
unsigned int baudrate)
@@ -37,7 +57,7 @@ static inline unsigned int ns16550_calc_divisor(unsigned int
clk,
return (clk / 16 / baudrate);
}
-static inline void INIT_LL(void)
+static inline void socfpga_uart_setup_ll(void)
{
unsigned int div = ns16550_calc_divisor(CONFIG_DEBUG_SOCFPGA_UART_CLOCK,
115200);
@@ -53,25 +73,19 @@ static inline void INIT_LL(void)
writel(FCRVAL, UART_BASE + FCR);
}
-#ifdef CONFIG_ARCH_SOCFPGA_ARRIA10
+#if defined(CONFIG_ARCH_SOCFPGA_CYCLONE5)
static inline void PUTC_LL(char c)
{
- /* Wait until there is space in the FIFO */
- while ((readl(UART_BASE + LSR) & LSR_THRE) == 0);
- /* Send the character */
- writel(c, UART_BASE + THR);
- /* Wait to make sure it hits the line, in case we die too soon. */
- while ((readl(UART_BASE + LSR) & LSR_THRE) == 0);
+ void __iomem *base = IOMEM(UART_BASE);
+
+ socfpga_gen5_uart_putc(base, c);
}
#else
static inline void PUTC_LL(char c)
{
- /* Wait until there is space in the FIFO */
- while ((readb(UART_BASE + LSR) & LSR_THRE) == 0);
- /* Send the character */
- writeb(c, UART_BASE + THR);
- /* Wait to make sure it hits the line, in case we die too soon. */
- while ((readb(UART_BASE + LSR) & LSR_THRE) == 0);
+ void __iomem *base = IOMEM(UART_BASE);
+
+ socfpga_uart_putc(base, c);
}
#endif
@@ -80,7 +94,7 @@ static inline unsigned int ns16550_calc_divisor(unsigned int
clk,
unsigned int baudrate) {
return -ENOSYS;
}
-static inline void INIT_LL(void) {}
+static inline void socfpga_uart_setup_ll(void) {}
static inline void PUTC_LL(char c) {}
#endif
#endif /* __MACH_SOCFPGA_DEBUG_LL_H__ */
--
2.46.0
