The devicetree files from the Enclustra BSP are outdated and not compatible with what barebox expects. Use the upstream SoC devicetree imported from Linux instead. For the board itself, we import the devicetree in the most recent posting[1] to the kernel mailing lists.
[1]: https://lore.kernel.org/all/20241116131025.114542-1-l.rubu...@gmail.com/ Co-developed-by: Ahmad Fatoum <ah...@a3f.at> Signed-off-by: Ahmad Fatoum <ah...@a3f.at> Signed-off-by: David Picard <david.pic...@clermont.in2p3.fr> --- arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts | 18 +-- arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi | 150 +++++++++++++++++++++++++ 2 files changed, 152 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts index 9e2f2c1af19e68c0c662f62bc154856f75df2510..2e69f33b030a144d08d55eacb01fd69b009f38e8 100644 --- a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts +++ b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts @@ -1,27 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2025 David Picard <david.pic...@clermont.in2p3.fr> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#include <arm/intel/socfpga/socfpga_cyclone5_mercury_sa2.dts> +#include "socfpga_cyclone5_mercury_sa2.dtsi" #include "socfpga.dtsi" / { chosen { - stdout-path = &uart0; - environment { compatible = "barebox,environment"; device-path = &mmc, "partname:1"; diff --git a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..73bd75fcf224fbf31fce27dda6566d4bfe37d624 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + * + * TODO: This whole file should be dropped, once the patches[1] are upstream + * and synced into barebox dts/src/arm. + * [1]: https://lore.kernel.org/all/20241116131025.114542-1-l.rubu...@gmail.com/ + */ + +#include <arm/intel/socfpga/socfpga_cyclone5.dtsi> + +/ { + model = "Enclustra Mercury+ SA2"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; +}; + +&osc1 { + clock-frequency = <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + status = "okay"; + + isl12020: rtc@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; + + atsha204a: crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns = <300>; + status = "disabled"; +}; + +&uart0 { + clock-frequency = <100000000>; +}; + +&mmc0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <10000000>; + + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@raw { + label = "Flash Raw"; + reg = <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + /delete-property/ mac-address; + phy-mode = "rgmii"; + phy-handle = <&phy3>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg = <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps = <1680>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + rxdv-skew-ps = <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps = <1860>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; -- 2.43.0
