Now that dma_alloc_coherent and dma_alloc_writecombine take an optional device parameter, let's take the dma_offset of the device into account if a device has been supplied.
This will allow supporting systems, where the CPU and other DMA masters, see the SDRAM at different addresses (i.e. has a dma-ranges in the DT). Signed-off-by: Ahmad Fatoum <[email protected]> --- Result of a discussion with Anis. Needs to be tested. --- arch/arm/cpu/mmu-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/mmu-common.c b/arch/arm/cpu/mmu-common.c index dd4c8f7de7d4..30a9dfbcb9c0 100644 --- a/arch/arm/cpu/mmu-common.c +++ b/arch/arm/cpu/mmu-common.c @@ -47,7 +47,7 @@ void *dma_alloc_map(struct device *dev, size = PAGE_ALIGN(size); ret = xmemalign(PAGE_SIZE, size); if (dma_handle) - *dma_handle = (dma_addr_t)ret; + *dma_handle = cpu_to_dma(ret); memset(ret, 0, size); dma_flush_range(ret, size); -- 2.47.3
