On 1/30/26 06:17, Sohaib Mohamed wrote: > Add RK3562 naneng combphy support for PCIe and USB3 modes with SSC, > CTLE, PLL configuration, and support for 24MHz/25MHz/100MHz reference > clocks. > NOTE: this commit is compile-tested Only. I tested only USB 2.0. > > Signed-off-by: Sohaib Mohamed <[email protected]>
Acked-by: Ahmad Fatoum <[email protected]> > --- > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 161 > +++++++++++++++++++++ > 1 file changed, 161 insertions(+) > > diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > index 7951a109f5..4a2e5f11ee 100644 > --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > @@ -402,6 +402,163 @@ static int rockchip_combphy_probe(struct device *dev) > return PTR_ERR_OR_ZERO(phy_provider); > } > > +static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) > +{ > + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; > + unsigned long rate; > + u32 val; > + > + switch (priv->type) { > + case PHY_TYPE_PCIE: > + /* Set SSC downward spread spectrum */ > + rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, > + PHYREG32_SSC_DOWNWARD << > PHYREG32_SSC_DIR_SHIFT, > + PHYREG32); > + > + rockchip_combphy_param_write(priv->phy_grf, > &cfg->con0_for_pcie, true); > + rockchip_combphy_param_write(priv->phy_grf, > &cfg->con1_for_pcie, true); > + rockchip_combphy_param_write(priv->phy_grf, > &cfg->con2_for_pcie, true); > + rockchip_combphy_param_write(priv->phy_grf, > &cfg->con3_for_pcie, true); > + break; > + case PHY_TYPE_USB3: > + /* Set SSC downward spread spectrum */ > + rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, > + PHYREG32_SSC_DOWNWARD << > PHYREG32_SSC_DIR_SHIFT, > + PHYREG32); > + > + /* Enable adaptive CTLE for USB3.0 Rx */ > + rockchip_combphy_updatel(priv, PHYREG15_CTLE_EN, > + PHYREG15_CTLE_EN, PHYREG15); > + > + /* Set PLL KVCO fine tuning signals */ > + rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, > + BIT(3), PHYREG33); > + > + /* Set PLL LPF R1 to su_trim[10:7]=1001 */ > + writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); > + > + /* Set PLL input clock divider 1/2 */ > + val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2); > + rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, > PHYREG6); > + > + /* Set PLL loop divider */ > + writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); > + > + /* Set PLL KVCO to min and set PLL charge pump current to max */ > + writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); > + > + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, > true); > + rockchip_combphy_param_write(priv->phy_grf, > &cfg->pipe_txcomp_sel, false); > + rockchip_combphy_param_write(priv->phy_grf, > &cfg->pipe_txelec_sel, false); > + rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, > true); > + break; > + default: > + dev_err(priv->dev, "incompatible PHY type\n"); > + return -EINVAL; > + } > + > + rate = clk_get_rate(priv->refclk); > + > + switch (rate) { > + case REF_CLOCK_24MHz: > + if (priv->type == PHY_TYPE_USB3) { > + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ > + val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, > + PHYREG15_SSC_CNT_VALUE); > + rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, > + val, PHYREG15); > + > + writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); > + } > + break; > + case REF_CLOCK_25MHz: > + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, > true); > + break; > + case REF_CLOCK_100MHz: > + rockchip_combphy_param_write(priv->phy_grf, > &cfg->pipe_clk_100m, true); > + if (priv->type == PHY_TYPE_PCIE) { > + /* Gate_tx_pck_sel length select for L1ss support */ > + rockchip_combphy_updatel(priv, PHYREG13_CKRCV_AMP0, > + PHYREG13_CKRCV_AMP0, > + PHYREG30); > + /* PLL KVCO tuning fine */ > + val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, > + PHYREG33_PLL_KVCO_VALUE); > + rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, > + val, PHYREG33); > + > + /* Enable controlling random jitter, aka RMJ */ > + writel(0x4, priv->mmio + PHYREG12); > + > + val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT; > + rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, > + val, PHYREG6); > + > + writel(0x32, priv->mmio + PHYREG18); > + writel(0xf0, priv->mmio + PHYREG11); > + } > + break; > + default: > + dev_err(priv->dev, "Unsupported rate: %lu\n", rate); > + return -EINVAL; > + } > + > + if (priv->ext_refclk) { > + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, > true); > + if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { > + val = PHYREG13_RESISTER_HIGH_Z << > PHYREG13_RESISTER_SHIFT; > + val |= PHYREG13_CKRCV_AMP0; > + rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, > val, > + PHYREG13); > + > + val = readl(priv->mmio + PHYREG14); > + val |= PHYREG14_CKRCV_AMP1; > + writel(val, priv->mmio + PHYREG14); > + } > + } > + > + if (priv->enable_ssc) { > + val = readl(priv->mmio + PHYREG8); > + val |= PHYREG8_SSC_EN; > + writel(val, priv->mmio + PHYREG8); > + } > + > + return 0; > +} > + > +static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { > + /* pipe-phy-grf */ > + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, > + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, > + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, > + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, > + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, > + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, > + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, > + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, > + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, > + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, > + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, > + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, > + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, > + .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, > + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, > + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, > + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, > + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, > + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, > +}; > + > +static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { > + .num_phys = 2, > + .phy_ids = { > + 0xff750000 > + }, > + .grfcfg = &rk3562_combphy_grfcfgs, > + .combphy_cfg = rk3562_combphy_cfg, > +}; > + > + > static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) > { > const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; > @@ -1055,6 +1212,10 @@ static const struct rockchip_combphy_cfg > rk3588_combphy_cfgs = { > }; > > static const struct of_device_id rockchip_combphy_of_match[] = { > + { > + .compatible = "rockchip,rk3562-naneng-combphy", > + .data = &rk3562_combphy_cfgs, > + }, > { > .compatible = "rockchip,rk3568-naneng-combphy", > .data = &rk3568_combphy_cfgs, > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
