From: Thomas Haemmerle <[email protected]> P_SIZE/T_SIZE are undocumented AXI-burst-size selectors: 1 = 128 byte, 2 = 256 byte. The driver inherited 256B from NXP downstream, which works for 1080p (stride 7680 B = 30 * 256 B) but breaks on narrower 32 bpp panels whose row byte count isn't a multiple of 256.
On an 800-pixel row at XRGB8888, stride = 3200 B = 12.5 * 256 B. The trailing partial burst is dropped and the panel shows a ~32-pixel-wide black strip at the right edge. 128B is a divisor of every common 32 bpp stride (3200, 3840, 5120, ...), so the gap disappears. Signed-off-by: Thomas Haemmerle <[email protected]> --- drivers/video/lcdif_kms.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/video/lcdif_kms.c b/drivers/video/lcdif_kms.c index 3a31633818..a113f3e681 100644 --- a/drivers/video/lcdif_kms.c +++ b/drivers/video/lcdif_kms.c @@ -216,18 +216,14 @@ static void lcdif_set_mode(struct lcdif_drm_private *lcdif, lcdif->base + LCDC_V8_CTRLDESCL0_1); /* - * Undocumented P_SIZE and T_SIZE register but those written in the - * downstream kernel those registers control the AXI burst size. As of - * now there are two known values: - * 1 - 128Byte - * 2 - 256Byte - * Downstream set it to 256B burst size to improve the memory - * efficiency so set it here too. + * P_SIZE/T_SIZE are undocumented AXI-burst-size selectors: + * 1 = 128 byte, 2 = 256 byte. Use 128B so any 32 bpp row divides + * into whole bursts; 256B on an 800-pixel row produces a partial + * trailing burst and a ~32-pixel black strip at the right edge. + * + * Stride is fixed to hdisplay * 4 (DRM_FORMAT_XRGB8888). */ - /* NOTE: Since this driver is currently fixed to DRM_FORMAT_XRGB8888 - * we asume a stride of vdisplay * 4 - */ - ctrl = CTRLDESCL0_3_P_SIZE(2) | CTRLDESCL0_3_T_SIZE(2) | + ctrl = CTRLDESCL0_3_P_SIZE(1) | CTRLDESCL0_3_T_SIZE(1) | CTRLDESCL0_3_PITCH(m->hdisplay * 4); writel(ctrl, lcdif->base + LCDC_V8_CTRLDESCL0_3); } -- 2.43.0
