Hello Philipp,
Hello Sascha,
On 5/7/25 10:22 AM, Philipp Zabel wrote:
> On Mi, 2025-05-07 at 09:25 +0200, Ahmad Fatoum wrote:
>> Hello Sascha,
>>
>> On 5/6/25 09:51, Sascha Hauer wrote:
>>> On Sun, Apr 27, 2025 at 03:44:53PM +0200, Ahmad Fatoum wrote:
>>
>>>> @@ -189,10 +200,10 @@ static int imx6q_ldb_prepare(struct imx_ldb_channel
>>>> *imx_ldb_ch, int di,
>>>> pixclk *= 2;
>>
>> This multiplication by 2 is only done for the single channel mode.
>
> TBH, I don't quite understand this. In the kernel, di_clk is calculated
> as drm_display_mode->clock * 1000 in either mode.
>
> Does this mean that the pixclk parameter passed to imx6q_ldb_prepare
> was 3.5 MHz here, resulting in the 7 MHz rate that ldb_di0_podf is set
> to after this multiplication?
>
>>>>
>>>> if (dual) {
>>>> - imx6q_set_clock(ldb, ipuno, dino, 0, pixclk);
>>>> - imx6q_set_clock(ldb, ipuno, dino, 1, pixclk);
>>>> + imx6q_set_clock(ldb, ipuno, dino, 0, pixclk * 7, pixclk);
>>>> + imx6q_set_clock(ldb, ipuno, dino, 1, pixclk * 7, pixclk);
>
> The di_clk:serial_clk ratio is 1:7 here, regardless of what happened to
> pixclk before.
This patch is indeed wrong and the regression is fixed now by
v2026.10.0, which contains commit 683819ecd972, a backport of the Linux
commit da321133b53 ("clk: divider: fix calculation of maximal parent
rate for a given divider").
Cheers,
Ahmad
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