On Saturday 15 September 2007 20:07:22 Larry Finger wrote: > Your comments may be correct; however, the fact remains that with a rev 4 > BCM4306, the original code > generates many, many machine checks on PPC architecture, and I get reads with > all ones on i386 > indicating that the read is invalid. These all occur before the firmware is > loaded. Making the > "gmode" bit mimic the behavior of the phy_connected variable of bcm43xx gets > rid of the problems on > both platforms.
Sure. But if you workaround this like that, you could as well get completely rid of the gmode bit, as you always force it on. But I think that's not what we want. The real fix is simple. See below. > The registers that error are not just the extended GPHY registers that caused > problems in the past, but all the PHY registers. Nobody is talking about the extG registers. > If you can suggest a reordering of the initialization that delays PHY setup > until the "magic step" > that eliminates this problem is done on/to the ssb backplane, I will be happy > to test it. I was > unable to find such a solution. There is no reordering needed. You just need to find out why phy->gmode was not set. I think it's set based on the have_gphy and have_bphy bits. So you need to look there why one of these is not set. That is the real cause of the issue. -- Greetings Michael. _______________________________________________ Bcm43xx-dev mailing list [email protected] https://lists.berlios.de/mailman/listinfo/bcm43xx-dev
