2010/2/27 Larry Finger <[email protected]>: > >> 3. Right after the SPROM is read, wl writes zeros to MMIO offsets >> 0x58 and 0x5c (32-bit), then does the PMU setup. These are not valid >> registers for ChipCommon and PCIE, but for 802.11, they fall directly >> into the DMA area! So, if these writes happened with the 802.11 core >> active, they are probably significant. > > That sounds promising. I think I found the section, which will have the > following specs: > > 1. If the Chip Common revision >= 20 > a. Save the current core index > a. Set core to chip common > a. Write 0 to GPIO Pullup (register 0x58) > a. Write 0 to GPIO Pulldown (register 0x5C) > a. Restore the original core > 1. If PMU Control Enabled > a. Init the PMU > ... > > A quick look ar the code suggests this should go into ssb_chipcommon_init() > just > after the return for not having a chip common. In addition, chip common will > already be selected, thus that part can be skipped. >
OK, I whipped up a quick test patch with changes found so far implemented. Please test if this improves the situation. -- Vista: [V]iruses, [I]ntruders, [S]pyware, [T]rojans and [A]dware. :-) _______________________________________________ Bcm43xx-dev mailing list [email protected] https://lists.berlios.de/mailman/listinfo/bcm43xx-dev
