Hello, I am using a Beaglebone Black. When i measured the number of PRU clock cycles needed for the execution of various assembler instructions, I found surprisingly large values for memory access. Here follows a list, in which one cycle corresponds to a delay of 5ns as expected:
Most operations, such as ADD,SUB,QBxx,MOV,JMP etc.: 1 cycle LBBO 1,2,4 Bytes from PRU DRAM: 3 cycles LBBO 8 Bytes from PRU DRAM: 4 cycles LBBO 12 Bytes from PRU DRAM: 5 cycles LBBO 16 Bytes from PRU DRAM: 6 cycles LBCO 4 Bytes from DDR: 43 cycles LBCO 8 Bytes from DDR: 44 cycles LBCO 12 Bytes from DDR: 45 cycles LBCO 16 Bytes from DDR: 46 cycles With PRU DRAM, i mean any addresses between 0x00000000 and 0x00004000 and the shared PRU RAM (12 kB starting from 0x00010000). Any other address i tried had the delay stated for "DDR". Can anybody confirm the long DDR (and other delays if possible) readout times that I have measured? Does anybody have an explanation for these large delays? Thanks in advance! Lenny -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/groups/opt_out.
