I think I have seen those on my scope during I2C transactions as well. They look like little shark fins that sometimes get high enough to be seen as a logic 1. They have no impact on the device as it's just the transition time between when the master is done transmitting the device address and starting to send data. The data line is released by the device but the master has not started to place data on the wire yet so the line starts to float back up via the pull-up. In your photo, it happens on the falling edge of the 9th clock bit and it's gone before the rising edge of the 10th clock so it's not being read as data.
Stronger pull-ups will just assist the runt in rising faster since the lower resistance allows the data line capacitance to be charged faster. On the scope you'd see the shark-fin start getting taller as you reduce the resistance. Your logic analyzer is just showing the brief time that the runt was interpreted as a logic 1 by the logic analyzer. Data isn't clocked in until SCL goes from low to high. I think what you are chasing there is a red herring. The Logic analyzer shows both data values being what they ought to be. -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/groups/opt_out.
