He's using a Saleae logic analyzer so no way to alter the ground lead. This isn't ringing, when you see it on a short time-base it's very clearly a period of time between bytes when the data line is released and begins to rise back up to the positive rail. It's often too short to trigger a logic high but sometimes with stiffer pull-ups it rises high enough to be viewed as a logic high before the data line is driven again.
As you say though, I really think it's not the issue involved here. It's not occurring while clock is high so it's not messing with start|stop and it's gone before the next clock edge so it's not getting read as data. -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/groups/opt_out.
