I apologize, a miss click posted that...full code below.
> *// enable ocp master.*LBCO r0, C4, 4, 4 > CLR r0, r0, 4 > SBCO r0, C4, 4, 4 > *// try to set gpio address* > > *// gpio on*mov r1, 0x4000 # gpio 0, bit 14, p9.29 > mov r0, 0x44E07194 # gpio 0 set register > SBBO r1, r0, 0, 4 > *// led on p9.26 light up here, devmem2 shows this address was set* > > *// readback*LBBO r1, r0, 0, 4 > *// readback matches!* > > *// gpio off*mov r1, 0x4000 # bit 14, p9.29 > mov r0, 0x44E07190 # gpio 0 clear register > SBBO r1, r0, 0, 4 > *// led on p9.26 shuts off here, devmem2 shows this address was set* > LBBO r1, r0, 0, 4 > *// readback matches* > > > *// try to set config address, P8.40*mov r1, 0x25 > mov r0, 0x44E108B8 > > *// devmem 2 says 0x44E108B8 = 0x5 (what i have it set to in dts)*SBBO > r1, r0, 0, 4 > *// devmem 2 says 0x44E108B8 is still 0x5!* > LBBO r1, r0, 0, 4 > *// readback doesn't match! r1 is now 0x5!* You had me excited, even though I'd tested this before, and have read in multiple places that it's not possible. :( --Brandon On Saturday, June 21, 2014 1:24:32 AM UTC-7, Brandon I wrote: > > "You have 100% full control over anything the PRU can access." > > This pru code seems to disproves this. The PRU cannot modify the > configuration registers. > > > // enable ocp master. > LBCO r0, C4, 4, 4 > CLR r0, r0, 4 > SBCO r0, C4, 4, 4 > > // turn on gpio > mov r1, 0x4000 > mov r0, 0x44E07194 > SBBO b, a, 0, 4 > // readback > LBBO b, a, 0, 4 > > // gpio off > mov b, 0x4000 > mov a, 0x44E07190 > SBBO b, a, 0, 4 > // readback > LBBO b, a, 0, 4 > > > > On Monday, May 19, 2014 2:36:51 PM UTC-7, Charles Steinkuehler wrote: >> >> On 5/19/2014 4:06 PM, Brandon I wrote: >> > The pin mux registers require privileged memory access, which is why >> > the kernel space is usually required. The pru can write these!? >> >> Of course. The PRU is directly wired into the on-chip bus, and bypasses >> all ARM side sanity checks like memory page access restrictions. You >> have 100% full control over anything the PRU can access, which is just >> about every significant chunk of hardware on the die except for: >> >> * SGX-530 GPU >> * AES & SHA crypto accelerator >> * USB >> * MMC >> >> Details are in the Interconnects section of the TRM (section 10), and >> remember: >> >> With great power comes great responsibility! >> >> -- >> Charles Steinkuehler >> cha...@steinkuehler.net >> > -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to beagleboard+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
