Great!

Thanks so much for the help.

Bill

On Sun, Nov 2, 2014 at 4:15 AM, TJF <[email protected]> wrote:

>
>
> Am Sonntag, 2. November 2014 01:40:22 UTC+1 schrieb Bill Gray:
>>
>> Am I correct in assuming that the low latency pins are specific to one or
>> the other PRU?  For example, should I assume that something like
>> "pr1_pru1_pru_r31_6" is a low latency input that is exclusively available
>> to PRU1?  Well, I suppose PRU0 might be able to read that pin as a regular
>> old GPIO, but I'm after low latency here.
>>
>
> Sounds good!
>
> I suppose by 'regular old GPIO' you mean accessing registers in the GPIO
> subsystem through the OCP master port. Both PRUSS can control all header
> pins that way (2 - 3 cycles latency).
>
> 'pr1_pru1_pru_r31_6' is on header P9 at pin 39 (CPU connector T3, ball#
> 46). Depending on the pinmuxing (the mode in the Control Module pad
> register at offset 0x8B8) it either can get controled as bit 12 in
> subsystem GPIO-2 by both PRUSS (mode 7 = gpio2-12). Or for low latency it's
> exclusive for PRU-1 and can be an input (mode 6 = pr1_pru1_pru_r31_6) or an
> output (mode 5 = pr1_pru1_pru_r30_6).
>
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-- 
Bill Gray
Velkess
415 407 7356

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