On 1/9/2015 3:09 AM, TJF wrote: > I'm not Jason. I'll answer, though. > > I have been looking at your presentation slides and am puzzled with Slide 25 >> "PRU low-latency I/Os". I notice that a couple of the pins are suffixed >> with 'PRU1_16 in' and 'PRU0_15 out 11 ---- 12 PRU0_14 out ' >> >> What is the significance of the in and out?
In and out for the PRU pins indicates the direction of the signal. The PRU direct I/O have unique buses for the input and output signals, so (for instance) a pin that can function as a direct PRU output cannot necessarily also function as a direct PRU input. The pins are labeled with the PRU core they are connected to (PRU0 or PRU1) and the register/direction they support (R31 = Inputs, R30 = outputs). >> Can the other GPIO pins be accessed by the PRU? > > A GPIO operates in a direction, either output or input. It's possible to > change the direction at run-time. > > All GPIO subsystems can get controlled over the OCP master port (2-3 PRU > cycles latency). There's significantly more overhead than 2-3 cycles. You only see 2-3 cycles of latency for the first few posted writes. Sustained writes or any reads have significantly longer latencies: https://github.com/machinekit/machinekit/blob/master/src/hal/drivers/hal_pru_generic/pru_generic.p#L135-L163 -- Charles Steinkuehler [email protected] -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
