I'm not an expert, and just learning myself... I found the examples in 'am335x_pru_package' on GitHub very useful, and was able to get them working on a 3.8 kernel.
DDR access will have additional latency but 5.8us sounds high. Is that for 1 LBBO instruction? How are you timing this (which timer)? What is the CPU doing during this time, if it is running 100% in a tight loop polling that same memory then CPU/PRU will be in contention, and that could cause excessive latency. Typically something like the pru interrupt is needed to let the cpu know that pru is done/ready etc. On Thursday, January 15, 2015 at 4:52:40 PM UTC-8, [email protected] wrote: > > > I see up to 5.8 microseconds of latency when the PRU is reading from DDR > memory. Is it possible to reduce this? I tried changing registers that > looked promising for giving the PRU priority but they didn't have a > noticeable effect. This is running on a Beaglebone black using a PRU timer > to measure the maximum time a LBBO from DDR takes.while the ARM is busy. > > > The examples I found for doing DMA from the PRU were all for older kernels > and wouldn't work with Linux 3.8.13. Is there an example I missed that > works with this kernel? > -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
