On Monday, August 24, 2015 at 5:39:54 PM UTC-7, Charles Steinkuehler wrote:
>
> On 8/24/2015 6:12 PM, Andrew P. Lentvorski wrote: 
> > I've been trying to hunt down the maximum frequency on the BeagleBone 
> Black 
> > GPIO pins. 
> > 
> > This *seems* to be dominated by the transaction latency across the L3/L4 
> > interconnect.  Fair enough.  So ... 
> > 
> > What's the latency number? 
> > 
> > I've *measured* about 166ns per transaction (I can create a roughly 3MHz 
> > toggle which is 2 pin flips which requires 6MTransactions/s which is 
> > 166.66ns per transaction).  But I don't know how to *calculate* that 
> number 
> > from the documentation. 
>
> I've measured 40 ns from the PRU.  I'm not sure if the CPU can match 
> this, but I'd be surprised if it couldn't. 
>

Well, there could be some silliness involving the fact that the memory is 
mmap'd in Linux.  A TLB access or something similar might be required that 
could add overhead.

This is a bit lower level than you'll find in most reference manuals, 
> and falls into the category of "if it's _really_ important to you, 
> contact the manufacturer and verify"...and I hope you're buying a 
> *LOT* of parts, because this is the sort of thing that is subject to 
> change with die revisions.  :) 
>

It actually surprises me that this information isn't documented.  However, 
I presume it's because most people using this high-end a processor really 
only use the peripherals.  The only thing most people really use the GPIO's 
for is generating interrupts.

I suspect I could live with things as they stand, but this is really going 
to make things ... annoying.

I may be better off just trying to do nasty things to the McSPI subsystem. 
 SPI really doesn't like bi-directional data lines, though.

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