On 6/29/2016 7:53 AM, Vincent lc wrote: > > @Charles > > So it's true if L4_Fast bus used to communicate with the PRU runs at 100 MHz > I > will be really interested in it. > If I have well understand it, that's mean that I have to load the data into > this > location > > PRU_ICSS 0x4A30_0000 0x4A37_FFFF 512KB > PRU-ICSSInstruction/Data/ControlSpace > > (extract from page 184 of the TRM : Table 2-4. L4 Fast Peripheral Memory Map > (continued) ) > > Previously, I was using this instruction to load my data into the PRU RAM > | > prussdrv_pru_write_memory(PRUSS0_PRU0_DATARAM,0,sequenceData,NUMBER_DATA); > | > > So now I have to replace it with > | > prussdrv_map_extmem(sequenceData); > | > Is its write ?
It depends on what you're trying to do. I don't typically use the PRU library stuff for anything other than getting the code running on the PRU, so I'm not the best person to ask. > (sequence Data is my array of data store define as is : > | > unsignedintsequenceData[NUMBER_DATA]; > | > > An other question is, in assembly, am I also supposed to load it from > 0x4A30_0000 address or there is a padding that I need to had because of the > PRU > mapping ? I'm not sure what you're asking. The PRU view of memory is documented in section 3.1.2, "Local Data Memory Map", along with the documentation for the PMAO register in the PRU CFG space. The ARM view of the PRU subsystem is documented in section 3.2, "Global Memory Map". > When you are saying : > > If you want to read data efficiently from DDR using the PRU, you > should use the LBBO command to read as large a block of data as > possible. > > > you mean use > | > LBBO (LBBO REG1,Rn2,OP(255),IM(124)) > | > > with IM=124 write ? Yes, the IM(124) value should be as large as possible to provide high-speed reads. The maximum value will depend on how large a block of free registers you can leave in your code. > Before I start to do so, have you got an idea of the "read latency effects" > that I have to expect in this specific case? The read latency will basically be the same whether you're reading one byte or the whole register file. That's why you want to read as much at one time as you can. The actual read latency will vary depending on the current state of the DDR memory (which pages are open) and how heavily the ARM core and other on-chip resources are using the DDR. -- Charles Steinkuehler [email protected] -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/c6dae5cb-178d-9acc-8a80-abb1cc99af6d%40steinkuehler.net. For more options, visit https://groups.google.com/d/optout.
