Thanks Robert!

Will try to keep everyone updated on here or reference developments on the 
"parallel" E2E thread.
  
Regards, jeff



On Friday, March 23, 2018 at 9:40:13 AM UTC-5, RobertCNelson wrote:
>
> On Fri, Mar 23, 2018 at 9:30 AM, Jeff Andich <[email protected] 
> <javascript:>> wrote: 
> > Hey Robert, 
> > 
> > The EEPROM is mostly board ID, serial number, and Ethernet MAC addresses 
> > right?  There isn't anything which is DRAM-specific in EEPROM, right? 
> > 
> > My understanding is the EEPROM contains the board ID which u-boot-spl 
> and 
> > u-boot use to customize the configurations for each specific board...   
> I 
> > understand that most of the board-specific changes are contained in the 
> > board.c file, but I'm wondering if there are other critical 
> configurations 
> > in the /arch/arm/mach-omap2 directory.  I also added some configurations 
> for 
> > our custom board type to the Kconfig in the mach-omap2 directory.  This 
> > looks to be menu options for a makemenuconfig GUI like for the kernel?? 
> > 
> > 
> > Have asked the TI folks on the above-referenced E2E post if there's a 
> DDR3 
> > test tool which can be run for an extended test. 
> > 
> > The guy on E2E who's having a similar issue,  implied that his firmware 
> > engineers already tuned the IO Delays.  Maybe it's something else?? 
> > 
> > I wonder who the people are who actually derive the IO delays (e.g. the 
> > GDELAY equtions) and tune them for boards like the BB-X15.. How does 
> that 
> > process work??  Maybe that's in TI's SPRAC44 ap note..  I still wonder, 
> how 
> > do you know when you've hit the sweet spot in terms of the optimum 
> values?? 
> > 
> > This doesn't appear to happen very frequently, but it's probably prudent 
> to 
> > get a handle on what makes it crop up.. 
>
> We got our magic numbers directly from TI.. 
>
> Thus, i'm not sure how they were generated... 
>
> Regards, 
>
> -- 
> Robert Nelson 
> https://rcn-ee.com/ 
>

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