Hi, I have read this nice ad for PRUs http://www.staroceans.org/documents/TI-sdk/spry264.pdf which states how deterministic the PRUs are,
"*each PRU has its own single-cycle I/O*" etc. Then I wanted details... http://processors.wiki.ti.com/index.php/Programmable_Realtime_Unit "Content is* no longer maintained and is being kept for reference only!* " http://processors.wiki.ti.com/index.php/PRU-ICSS "Please note as of Wednesday, August 15th, 2018 this wiki *has been set to read only*." http://processors.wiki.ti.com/index.php/PRU_Read_Latencies "The PRU write instruction is a fire-and-forget command that executes in *~*1 cycle" *that tilde...* "The read latency values at the following links are *considered* "best-case," accounting for the 2 cycle instruction and interconnect introduced *latency*". *best case....* Possibly, there is some doc which states min/max execution times? Deterministic or not? etc, etc. *Not found. Just not found.* ----------------------------------------------- I do not want to be pessimistic.... but neither I want to reverse-engineer these "deteministic" units, that do not really look that-deterministic. And that docs obsolete or missing??? What is it all about? -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to beagleboard+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/8976d66c-9bb4-40b9-aec9-b33874d42b99%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
