Hi there
I want to send some data to a micro controller with a beaglebone black (beagle bone is master). As shown in the picture, the delay between falling edge of cs and first rising edge of clock is too much. could you please tell me how to decrease it? the image is taken from a logic analyzer which its sampling rate is lower than SPI bitrate. thanks a lot. [image: cs.PNG] -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/7bc65e7a-d9b0-4a24-b622-186f5a22a9d7%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
