This is from the TI FAQ on the PRU: Does the PRU-ICSS/ PRU_ICSSG Support Interrupts?
Yes,but not in the same way that most cores support interrupts.The PRU-ICSS/ PRU_ICSSG contains an interrupt controller that can map 64 system events down to two flags that are set in a PRU core register (bits 30 and 31 in core register R31).The PRU core can then check each of these flags in a single cycle to see if an event has occurred.These flags can either be polled upon or checked periodically (dependent on what makes the most sense for the use case).The PRU-ICSS/ PRU_ICSSG interrupt controller does not support jumping the program counter of the PRU core to a pre-determined function when an event occurs. The other PRU can be one of these 64 events that sets a bit. Whether it makes more sense to use the bits in R31 or shared memory will depend upon your application. Shared memory would allow you to queue up more data than just a single bit, but a larger message could take more time to process. This is a design decision you will have to make. -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/5a29e2b2-dbb8-4819-b65b-8899c3a17324%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
