We should allocate register when we firstly visit ExtractElement instruction, as we may refer the value before we visit that instruction at the emit instruction pass.
The case which trigger this corner case is as below: Clang/llvm may generate some code similar to the following IRs: ... (there is no definition of %7) br label 2 label1: %10 = add %7, %6 ... ret label2: %7 = ... br label1 The value %7 is assigned after label2 but is referred at label1. >From the control flow, the IRs is valid. As the reference will be executed after the assignment. Signed-off-by: Zhigang Gong <[email protected]> --- backend/src/llvm/llvm_gen_backend.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp index 1316d4b..bfba825 100644 --- a/backend/src/llvm/llvm_gen_backend.cpp +++ b/backend/src/llvm/llvm_gen_backend.cpp @@ -1842,8 +1842,7 @@ namespace gbe } } - void GenWriter::regAllocateExtractElement(ExtractElementInst &I) {} - void GenWriter::emitExtractElement(ExtractElementInst &I) { + void GenWriter::regAllocateExtractElement(ExtractElementInst &I) { Value *vec = I.getVectorOperand(); const Value *index = I.getIndexOperand(); const ConstantInt *c = dyn_cast<ConstantInt>(index); @@ -1852,6 +1851,9 @@ namespace gbe regTranslator.newValueProxy(vec, &I, i, 0); } + void GenWriter::emitExtractElement(ExtractElementInst &I) { + } + void GenWriter::regAllocateShuffleVectorInst(ShuffleVectorInst &I) {} void GenWriter::emitShuffleVectorInst(ShuffleVectorInst &I) {} -- 1.7.9.5 _______________________________________________ Beignet mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/beignet
