Forgot add the these file to patch "[PATCH 8/8] SKL: fix skl LD fail.", and I have send out the new version, thanks.
> -----Original Message----- > From: He Junyan [mailto:junyan...@inbox.com] > Sent: Friday, January 30, 2015 10:29 > To: Yang, Rong R; beignet@lists.freedesktop.org > Subject: Re: [Beignet] [PATCH 1/8] SKL: Add skl pci ids and device. > > Hi, > > It seems that gen9_context.hpp and gen9_context.cpp are lost and can not > compile. > > > On 2015年01月29日 16:16, Yang Rong wrote: > > SKL add the new GT4 type device. > > > > Signed-off-by: Yang Rong <rong.r.y...@intel.com> > > --- > > src/cl_device_data.h | 45 +++++++++++++++++++ > > src/cl_device_id.c | 122 > +++++++++++++++++++++++++++++++++++++++++++++++++-- > > 2 files changed, 164 insertions(+), 3 deletions(-) > > > > diff --git a/src/cl_device_data.h b/src/cl_device_data.h > > index 0d25ca4..d6f8209 100644 > > --- a/src/cl_device_data.h > > +++ b/src/cl_device_data.h > > @@ -230,5 +230,50 @@ > > #define IS_BROADWELL(devid) (IS_BRW_GT1(devid) || > IS_BRW_GT2(devid) || IS_BRW_GT3(devid)) > > #define IS_GEN8(devid) IS_BROADWELL(devid) > > > > +/* SKL */ > > +#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 /* Intel(R) Skylake > ULT - GT1 */ > > +#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916 /* Intel(R) Skylake > ULT - GT2 */ > > +#define PCI_CHIP_SKYLAKE_ULT_GT3 0x1926 /* Intel(R) Skylake > ULT - GT3 */ > > +#define PCI_CHIP_SKYLAKE_ULT_GT2F 0x1921 /* Intel(R) Skylake > ULT - GT2F */ > > +#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Intel(R) Skylake > ULX - GT1 */ > > +#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E /* Intel(R) Skylake > ULX - GT2 */ > > +#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902 /* Intel(R) > Skylake Desktop - GT1 */ > > +#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912 /* Intel(R) > Skylake Desktop - GT2 */ > > +#define PCI_CHIP_SKYLAKE_HALO_GT1 0x190B /* Intel(R) Skylake > HALO - GT1 */ > > +#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B /* Intel(R) Skylake > HALO - GT2 */ > > +#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Intel(R) Skylake > HALO - GT3 */ > > +#define PCI_CHIP_SKYLAKE_HALO_GT4 0x193B /* Intel(R) Skylake > HALO - GT4 */ > > +#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Intel(R) Skylake > Server - GT1 */ > > +#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A /* Intel(R) Skylake > Server - GT2 */ > > +#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192A /* Intel(R) Skylake > Server - GT3 */ > > +#define PCI_CHIP_SKYLAKE_SRV_GT4 0x193A /* Intel(R) Skylake > Server - GT4 */ > > + > > +#define IS_SKL_GT1(devid) \ > > + (devid == PCI_CHIP_SKYLAKE_ULT_GT1 || \ > > + devid == PCI_CHIP_SKYLAKE_ULX_GT1 || \ > > + devid == PCI_CHIP_SKYLAKE_DT_GT1 || \ > > + devid == PCI_CHIP_SKYLAKE_HALO_GT1 || \ > > + devid == PCI_CHIP_SKYLAKE_SRV_GT1) > > + > > +#define IS_SKL_GT2(devid) \ > > + (devid == PCI_CHIP_SKYLAKE_ULT_GT2 || \ > > + devid == PCI_CHIP_SKYLAKE_ULT_GT2F || \ > > + devid == PCI_CHIP_SKYLAKE_ULX_GT2 || \ > > + devid == PCI_CHIP_SKYLAKE_DT_GT2 || \ > > + devid == PCI_CHIP_SKYLAKE_HALO_GT2 || \ > > + devid == PCI_CHIP_SKYLAKE_SRV_GT2) > > + > > +#define IS_SKL_GT3(devid) \ > > + (devid == PCI_CHIP_SKYLAKE_ULT_GT3 || \ > > + devid == PCI_CHIP_SKYLAKE_HALO_GT3 || \ > > + devid == PCI_CHIP_SKYLAKE_SRV_GT3) > > + > > +#define IS_SKL_GT4(devid) \ > > + (devid == PCI_CHIP_SKYLAKE_HALO_GT4 || \ > > + devid == PCI_CHIP_SKYLAKE_SRV_GT4) > > + > > +#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || IS_SKL_GT2(devid) || > IS_SKL_GT3(devid) || IS_SKL_GT4(devid)) > > +#define IS_GEN9(devid) IS_SKYLAKE(devid) > > + > > #endif /* __CL_DEVICE_DATA_H__ */ > > > > diff --git a/src/cl_device_id.c b/src/cl_device_id.c > > index 3032a38..9d83ab2 100644 > > --- a/src/cl_device_id.c > > +++ b/src/cl_device_id.c > > @@ -140,6 +140,51 @@ static struct _cl_device_id intel_brw_gt3_device = > { > > #include "cl_gen75_device.h" > > }; > > > > +/* XXX we clone brw now */ > > +static struct _cl_device_id intel_skl_gt1_device = { > > + INIT_ICD(dispatch) > > + .max_compute_unit = 6, > > + .max_thread_per_unit = 7, > > + .sub_slice_count = 2, > > + .max_work_item_sizes = {512, 512, 512}, > > + .max_work_group_size = 512, > > + .max_clock_frequency = 1000, > > +#include "cl_gen75_device.h" > > +}; > > + > > +static struct _cl_device_id intel_skl_gt2_device = { > > + INIT_ICD(dispatch) > > + .max_compute_unit = 24, > > + .max_thread_per_unit = 7, > > + .sub_slice_count = 3, > > + .max_work_item_sizes = {512, 512, 512}, > > + .max_work_group_size = 512, > > + .max_clock_frequency = 1000, > > +#include "cl_gen75_device.h" > > +}; > > + > > +static struct _cl_device_id intel_skl_gt3_device = { > > + INIT_ICD(dispatch) > > + .max_compute_unit = 48, > > + .max_thread_per_unit = 7, > > + .sub_slice_count = 6, > > + .max_work_item_sizes = {512, 512, 512}, > > + .max_work_group_size = 512, > > + .max_clock_frequency = 1000, > > +#include "cl_gen75_device.h" > > +}; > > + > > +static struct _cl_device_id intel_skl_gt4_device = { > > + INIT_ICD(dispatch) > > + .max_compute_unit = 72, > > + .max_thread_per_unit = 7, > > + .sub_slice_count = 9, > > + .max_work_item_sizes = {512, 512, 512}, > > + .max_work_group_size = 512, > > + .max_clock_frequency = 1000, > > +#include "cl_gen75_device.h" > > +}; > > + > > > > LOCAL cl_device_id > > cl_get_gt_device(void) > > @@ -378,6 +423,62 @@ brw_gt3_break: > > ret = &intel_brw_gt3_device; > > break; > > > > + case PCI_CHIP_SKYLAKE_ULT_GT1: > > + DECL_INFO_STRING(skl_gt1_break, intel_skl_gt1_device, > name, "Intel(R) HD Graphics Skylake ULT GT1"); > > + case PCI_CHIP_SKYLAKE_ULX_GT1: > > + DECL_INFO_STRING(skl_gt1_break, intel_skl_gt1_device, > name, "Intel(R) HD Graphics Skylake ULX GT1"); > > + case PCI_CHIP_SKYLAKE_DT_GT1: > > + DECL_INFO_STRING(skl_gt1_break, intel_skl_gt1_device, > name, "Intel(R) HD Graphics Skylake Desktop GT1"); > > + case PCI_CHIP_SKYLAKE_HALO_GT1: > > + DECL_INFO_STRING(skl_gt1_break, intel_skl_gt1_device, > name, "Intel(R) HD Graphics Skylake Halo GT1"); > > + case PCI_CHIP_SKYLAKE_SRV_GT1: > > + DECL_INFO_STRING(skl_gt1_break, intel_skl_gt1_device, > name, "Intel(R) HD Graphics Skylake Server GT1"); > > +skl_gt1_break: > > + intel_skl_gt1_device.vendor_id = device_id; > > + intel_skl_gt1_device.platform = intel_platform; > > + ret = &intel_skl_gt1_device; > > + break; > > + > > + case PCI_CHIP_SKYLAKE_ULT_GT2: > > + DECL_INFO_STRING(skl_gt2_break, intel_skl_gt2_device, > name, "Intel(R) HD Graphics Skylake ULT GT2"); > > + case PCI_CHIP_SKYLAKE_ULT_GT2F: > > + DECL_INFO_STRING(skl_gt2_break, intel_skl_gt2_device, > name, "Intel(R) HD Graphics Skylake ULT GT2F"); > > + case PCI_CHIP_SKYLAKE_ULX_GT2: > > + DECL_INFO_STRING(skl_gt2_break, intel_skl_gt2_device, > name, "Intel(R) HD Graphics Skylake ULX GT2"); > > + case PCI_CHIP_SKYLAKE_DT_GT2: > > + DECL_INFO_STRING(skl_gt2_break, intel_skl_gt2_device, > name, "Intel(R) HD Graphics Skylake Desktop GT2"); > > + case PCI_CHIP_SKYLAKE_HALO_GT2: > > + DECL_INFO_STRING(skl_gt2_break, intel_skl_gt2_device, > name, "Intel(R) HD Graphics Skylake Halo GT2"); > > + case PCI_CHIP_SKYLAKE_SRV_GT2: > > + DECL_INFO_STRING(skl_gt2_break, intel_skl_gt2_device, > name, "Intel(R) HD Graphics Skylake Server GT2"); > > +skl_gt2_break: > > + intel_skl_gt2_device.vendor_id = device_id; > > + intel_skl_gt2_device.platform = intel_platform; > > + ret = &intel_skl_gt2_device; > > + break; > > + > > + case PCI_CHIP_SKYLAKE_ULT_GT3: > > + DECL_INFO_STRING(skl_gt3_break, intel_skl_gt3_device, > name, "Intel(R) HD Graphics Skylake ULT GT3"); > > + case PCI_CHIP_SKYLAKE_HALO_GT3: > > + DECL_INFO_STRING(skl_gt3_break, intel_skl_gt3_device, > name, "Intel(R) HD Graphics Skylake Halo GT3"); > > + case PCI_CHIP_SKYLAKE_SRV_GT3: > > + DECL_INFO_STRING(skl_gt3_break, intel_skl_gt3_device, > name, "Intel(R) HD Graphics Skylake Server GT3"); > > +skl_gt3_break: > > + intel_skl_gt3_device.vendor_id = device_id; > > + intel_skl_gt3_device.platform = intel_platform; > > + ret = &intel_skl_gt3_device; > > + break; > > + > > + case PCI_CHIP_SKYLAKE_HALO_GT4: > > + DECL_INFO_STRING(skl_gt4_break, intel_skl_gt4_device, > name, "Intel(R) HD Graphics Skylake Halo GT4"); > > + case PCI_CHIP_SKYLAKE_SRV_GT4: > > + DECL_INFO_STRING(skl_gt4_break, intel_skl_gt4_device, > name, "Intel(R) HD Graphics Skylake Server GT4"); > > +skl_gt4_break: > > + intel_skl_gt4_device.vendor_id = device_id; > > + intel_skl_gt4_device.platform = intel_platform; > > + ret = &intel_skl_gt4_device; > > + break; > > + > > case PCI_CHIP_SANDYBRIDGE_BRIDGE: > > case PCI_CHIP_SANDYBRIDGE_GT1: > > case PCI_CHIP_SANDYBRIDGE_GT2: > > @@ -503,7 +604,11 @@ cl_get_device_info(cl_device_id device, > > device != &intel_hsw_gt3_device && > > device != &intel_brw_gt1_device && > > device != &intel_brw_gt2_device && > > - device != &intel_brw_gt3_device > > + device != &intel_brw_gt3_device && > > + device != &intel_skl_gt1_device && > > + device != &intel_skl_gt2_device && > > + device != &intel_skl_gt3_device && > > + device != &intel_skl_gt4_device > > )) > > return CL_INVALID_DEVICE; > > > > @@ -608,7 +713,11 @@ cl_device_get_version(cl_device_id device, cl_int > *ver) > > device != &intel_hsw_gt3_device && > > device != &intel_brw_gt1_device && > > device != &intel_brw_gt2_device && > > - device != &intel_brw_gt3_device)) > > + device != &intel_brw_gt3_device && > > + device != &intel_skl_gt1_device && > > + device != &intel_skl_gt2_device && > > + device != &intel_skl_gt3_device && > > + device != &intel_skl_gt4_device)) > > return CL_INVALID_DEVICE; > > if (ver == NULL) > > return CL_SUCCESS; > > @@ -622,6 +731,9 @@ cl_device_get_version(cl_device_id device, cl_int > *ver) > > } else if (device == &intel_brw_gt1_device || device == > &intel_brw_gt2_device > > || device == &intel_brw_gt3_device) { > > *ver = 8; > > + } else if (device == &intel_skl_gt1_device || device == > &intel_skl_gt2_device > > + || device == &intel_skl_gt3_device || device == > &intel_skl_gt4_device) { > > + *ver = 9; > > } else > > return CL_INVALID_VALUE; > > > > @@ -703,7 +815,11 @@ cl_get_kernel_workgroup_info(cl_kernel kernel, > > device != &intel_hsw_gt3_device && > > device != &intel_brw_gt1_device && > > device != &intel_brw_gt2_device && > > - device != &intel_brw_gt3_device)) > > + device != &intel_brw_gt3_device && > > + device != &intel_skl_gt1_device && > > + device != &intel_skl_gt2_device && > > + device != &intel_skl_gt3_device && > > + device != &intel_skl_gt4_device)) > > return CL_INVALID_DEVICE; > > > > CHECK_KERNEL(kernel); > > _______________________________________________ Beignet mailing list Beignet@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/beignet
