You can add no MMU to the complaints list , Arm chips that do include it use 20-25% of the die for it and are many times more expensive for the same performance as non MMU models.
Ben From: [email protected] [mailto:[email protected]] On Behalf Of Jonathan S. Shapiro Sent: Sunday, August 15, 2010 3:57 AM To: Discussions about the BitC language Subject: Re: [bitc-dev] Bitc and Simd On Sat, Aug 14, 2010 at 10:50 AM, orthochronous <[email protected]> wrote: Additionally the NEON unit on ARM uses only the L2 cache, requiring explicitly making the L1 cache coherent with L2 before accessing any of the data in the main part of the CPU... Good to know that ARM is consistent at something. They're developing deep expertise at fucking up concurrency. Weak memory consistency, weak cache coherency, and (until recently) a non-antialiased virtual cache. Could somebody please form a chip company that has architects on staff!
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