On Tue, Jul 16, 2013 at 10:43 AM, Sandro Magi <[email protected]>wrote:
> I'm not sure what you're referring to above. Can you elaborate? There's > nothing > so complicated in the paper that I can see. The CHICKEN collector in > particular is almost as trivial as mark-sweep. > The basic structure of on-the-fly tracing designs is to add read/write barriers to all memory access. These barriers are very undesirable, making memory use in your program slower. The overview paper in which CHICKEN was reviewed did not describe it's design in detail. Refer to the STOPLESS paper for a more complete explanation of their techniques, most of which apply to CHICKEN as well. There you can see a more complete description of their 'soft-handshake' system for asking threads to voluntarily switch between different modes, and in turn only uses barriers during certain (prep and copy) phases (see, 3.2.1 System Phases). This is the double-code-paths cost I was referring to, because if you want a version of the code completely without barrier checks, then you must have two versions of the code instantiated and switch between them. Another alternative is to always a barrier test which can be skipped with only modest cost. http://www.cs.technion.ac.il/~erez/Papers/stopless.pdf Aside from the dual-code paths/modes, another real-world problem with trying to turn the barrier on and off is that it only provides efficiency benefits if there are significant periods where the barrier can be off. For these and other reasons, I remain impressed by STOPLESS/CHICKEN yet cautious about drawing conclusions for real-world systems. These are research only, and we can't properly evaluate them without production implementations. --- In comparison, Azul research approached the problem differently. Instead they attacked the write-barrier cost itself, trying to make it cheap enough to leave on always. Their "Pauseless GC Algorithm" used custom CPU hardware with custom instructions designed to optimize the write barrier. The more recent C4 design (the basis for JVM Azul-Zing) uses page-guarding supported by the x86 MMU to achieve a similar (though not equivalent) fast write barrier. http://paperhub.s3.amazonaws.com/d14661878f7811e5ee9c43de88414e86.pdf https://www.usenix.org/legacy/events/vee05/full_papers/p46-click.pdf
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