tree 98b924f6a325804ba9304eb3793faf40fab39118
parent 2ffcaa19678e84d8f0a01e99881d3b661cce5859
author Andi Kleen <[EMAIL PROTECTED]> Tue Apr 12 08:25:41 2005
committer Linus Torvalds <[EMAIL PROTECTED]> Tue Apr 12 08:25:41 2005
[PATCH] x86_64: Always use CPUID 80000008 to figure out MTRR address space size
It doesn't make sense to only do this only for AMD K8.
This would support future CPUs with extended address spaces properly.
For i386 and x86-64
Cc: <[EMAIL PROTECTED]>
Signed-off-by: Andi Kleen <[EMAIL PROTECTED]>
Signed-off-by: Andrew Morton <[EMAIL PROTECTED]>
Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
main.c | 49 +++++++++++++++----------------------------------
1 files changed, 15 insertions(+), 34 deletions(-)
Index: arch/i386/kernel/cpu/mtrr/main.c
===================================================================
--- 73f299aaed1e5a9a5c2e9b826352c46391df40fc/arch/i386/kernel/cpu/mtrr/main.c
(mode:100644 sha1:2fa10c68a961da58a6ee9a466c4a801d5299313d)
+++ 98b924f6a325804ba9304eb3793faf40fab39118/arch/i386/kernel/cpu/mtrr/main.c
(mode:100644 sha1:a8b2b69dd33ae79e2c75a33df1d090332a9bb445)
@@ -614,40 +614,21 @@
mtrr_if = &generic_mtrr_ops;
size_or_mask = 0xff000000; /* 36 bits */
size_and_mask = 0x00f00000;
-
- switch (boot_cpu_data.x86_vendor) {
- case X86_VENDOR_AMD:
- /* The original Athlon docs said that
- total addressable memory is 44 bits wide.
- It was not really clear whether its MTRRs
- follow this or not. (Read: 44 or 36 bits).
- However, "x86-64_overview.pdf" explicitly
- states that "previous implementations support
- 36 bit MTRRs" and also provides a way to
- query the width (in bits) of the physical
- addressable memory on the Hammer family.
- */
- if (boot_cpu_data.x86 == 15
- && (cpuid_eax(0x80000000) >= 0x80000008)) {
- u32 phys_addr;
- phys_addr = cpuid_eax(0x80000008) & 0xff;
- size_or_mask =
- ~((1 << (phys_addr - PAGE_SHIFT)) - 1);
- size_and_mask = ~size_or_mask & 0xfff00000;
- }
- /* Athlon MTRRs use an Intel-compatible interface for
- * getting and setting */
- break;
- case X86_VENDOR_CENTAUR:
- if (boot_cpu_data.x86 == 6) {
- /* VIA Cyrix family have Intel style MTRRs, but
don't support PAE */
- size_or_mask = 0xfff00000; /* 32 bits */
- size_and_mask = 0;
- }
- break;
-
- default:
- break;
+
+ /* This is an AMD specific MSR, but we assume(hope?) that
+ Intel will implement it to when they extend the address
+ bus of the Xeon. */
+ if (cpuid_eax(0x80000000) >= 0x80000008) {
+ u32 phys_addr;
+ phys_addr = cpuid_eax(0x80000008) & 0xff;
+ size_or_mask = ~((1 << (phys_addr - PAGE_SHIFT)) - 1);
+ size_and_mask = ~size_or_mask & 0xfff00000;
+ } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
+ boot_cpu_data.x86 == 6) {
+ /* VIA C* family have Intel style MTRRs, but
+ don't support PAE */
+ size_or_mask = 0xfff00000; /* 32 bits */
+ size_and_mask = 0;
}
} else {
switch (boot_cpu_data.x86_vendor) {
-
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